文件名称:design

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 2.65mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 唐*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

基于cycloneII系列FPGA实现信号等精度测量频率、相位、周期-Realization precision measurement frequency, phase, period
(系统自动生成,下载前可以参看下载内容)

下载文件列表

design\count.vhd

......\count.vhd.bak

......\db\altsyncram_0hq1.tdf

......\..\altsyncram_4cp3.tdf

......\..\altsyncram_8cp3.tdf

......\..\altsyncram_8kq1.tdf

......\..\altsyncram_akq1.tdf

......\..\altsyncram_g7p3.tdf

......\..\altsyncram_gfp3.tdf

......\..\altsyncram_ifp3.tdf

......\..\altsyncram_k7p3.tdf

......\..\altsyncram_sap3.tdf

......\..\altsyncram_sgq1.tdf

......\..\altsyncram_uap3.tdf

......\..\cmpr_5cc.tdf

......\..\cmpr_9cc.tdf

......\..\cmpr_bcc.tdf

......\..\cmpr_ccc.tdf

......\..\cmpr_dcc.tdf

......\..\cntr_1ci.tdf

......\..\cntr_3ci.tdf

......\..\cntr_gui.tdf

......\..\cntr_pdi.tdf

......\..\cntr_qdi.tdf

......\..\cntr_sbi.tdf

......\..\cntr_u4j.tdf

......\..\decode_4oa.tdf

......\..\decode_rqf.tdf

......\..\design.asm.qmsg

......\..\design.asm_labs.ddb

......\..\design.atom.rvd

......\..\design.atom_map.rvd

......\..\design.cbx.xml

......\..\design.cmp.bpm

......\..\design.cmp.cdb

......\..\design.cmp.ecobp

......\..\design.cmp.hdb

......\..\design.cmp.kpt

......\..\design.cmp.logdb

......\..\design.cmp.rdb

......\..\design.cmp.tdb

......\..\design.cmp0.ddb

......\..\design.cmp2.ddb

......\..\design.cmp_merge.kpt

......\..\design.db_info

......\..\design.eco.cdb

......\..\design.eds_overflow

......\..\design.fit.qmsg

......\..\design.hier_info

......\..\design.hif

......\..\design.map.bpm

......\..\design.map.cdb

......\..\design.map.ecobp

......\..\design.map.hdb

......\..\design.map.kpt

......\..\design.map.logdb

......\..\design.map.qmsg

......\..\design.map_bb.cdb

......\..\design.map_bb.hdb

......\..\design.map_bb.hdbx

......\..\design.map_bb.logdb

......\..\design.merge.qmsg

......\..\design.pre_map.cdb

......\..\design.pre_map.hdb

......\..\design.psp

......\..\design.rpp.qmsg

......\..\design.rtlv.hdb

......\..\design.rtlv_sg.cdb

......\..\design.rtlv_sg_swap.cdb

......\..\design.sgate.rvd

......\..\design.sgate_sm.rvd

......\..\design.sgdiff.cdb

......\..\design.sgdiff.hdb

......\..\design.sim.cvwf

......\..\design.sim.hdb

......\..\design.sim.qmsg

......\..\design.sim.rdb

......\..\design.sim_ori.vwf

......\..\design.sld_design_entry.sci

......\..\design.sld_design_entry_dsc.sci

......\..\design.syn_hier_info

......\..\design.tan.qmsg

......\..\design.tis_db_list.ddb

......\..\design.tmw_info

......\..\mux_4kb.tdf

......\..\mux_6kb.tdf

......\..\mux_9oc.tdf

......\..\mux_qlb.tdf

......\..\mux_rlb.tdf

......\..\prev_cmp_design.asm.qmsg

......\..\prev_cmp_design.fit.qmsg

......\..\prev_cmp_design.map.qmsg

......\..\prev_cmp_design.merge.qmsg

......\..\prev_cmp_design.qmsg

......\..\prev_cmp_design.sim.qmsg

......\..\prev_cmp_design.tan.qmsg

......\..\wed.wsf

......\design.asm.rpt

......\design.cdf

......\design.done

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