文件名称:I2C
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FPGA数字电子系统设计与开发实例I2C UART VGA USB,可编程器件开发通用模块-FPGA digital electronic system design and development examples I2C UART VGA USB, programmable device of common modules
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下载文件列表
I2C\automake.log
...\coregen.log
...\coregen.prj
...\I2C.dhp
...\I2C.npl
...\i2c_master_bit_ctrl.cmd_log
...\i2c_master_bit_ctrl.lso
...\i2c_master_bit_ctrl.ngc
...\i2c_master_bit_ctrl.ngr
...\i2c_master_bit_ctrl.prj
...\i2c_master_bit_ctrl.stx
...\i2c_master_bit_ctrl.syr
...\i2c_master_bit_ctrl.v
...\i2c_master_bit_ctrl_vhdl.prj
...\i2c_master_byte_ctrl.cmd_log
...\i2c_master_byte_ctrl.lso
...\i2c_master_byte_ctrl.ngc
...\i2c_master_byte_ctrl.ngr
...\i2c_master_byte_ctrl.prj
...\i2c_master_byte_ctrl.stx
...\i2c_master_byte_ctrl.syr
...\i2c_master_byte_ctrl.v
...\i2c_master_byte_ctrl_vhdl.prj
...\i2c_master_defines.v
...\i2c_master_top.cmd_log
...\i2c_master_top.lso
...\i2c_master_top.ngc
...\i2c_master_top.ngr
...\i2c_master_top.prj
...\i2c_master_top.stx
...\i2c_master_top.syr
...\i2c_master_top.v
...\i2c_master_top_vhdl.prj
...\i2c_slave_model.fdo
...\i2c_slave_model.ndo
...\i2c_slave_model.udo
...\i2c_slave_model.v
...\prjname.lso
...\timescale.v
...\transcript
...\tst_bench_top.v
...\wb_master_model.v
...\__projnav.log
...\.........\coregen.rsp
...\.........\I2C.gfl
...\.........\I2C_flowplus.gfl
...\.........\i2c_master_bit_ctrl.xst
...\.........\i2c_master_byte_ctrl.xst
...\.........\i2c_master_top.xst
...\.........\runXst_tcl.rsp
...\.........\xst_sprjTOstx_tcl.rsp
...\xst\work\hdllib.ref
...\...\....\vlg67\i2c_master_top.bin
...\...\....\...5C\i2c_master_byte_ctrl.bin
...\...\....\...07\i2c_master_bit_ctrl.bin
...\work\_info
...\....\i2c_slave_model\verilog.asm
...\....\...............\_primary.dat
...\....\...............\_primary.vhd
...\....\glbl\verilog.asm
...\....\....\_primary.dat
...\....\....\_primary.vhd
...\xst\work\vlg67
...\...\....\vlg5C
...\...\....\vlg07
...\...\work
...\work\i2c_slave_model
...\....\glbl
...\__projnav
...\xst
...\work
I2C
...\coregen.log
...\coregen.prj
...\I2C.dhp
...\I2C.npl
...\i2c_master_bit_ctrl.cmd_log
...\i2c_master_bit_ctrl.lso
...\i2c_master_bit_ctrl.ngc
...\i2c_master_bit_ctrl.ngr
...\i2c_master_bit_ctrl.prj
...\i2c_master_bit_ctrl.stx
...\i2c_master_bit_ctrl.syr
...\i2c_master_bit_ctrl.v
...\i2c_master_bit_ctrl_vhdl.prj
...\i2c_master_byte_ctrl.cmd_log
...\i2c_master_byte_ctrl.lso
...\i2c_master_byte_ctrl.ngc
...\i2c_master_byte_ctrl.ngr
...\i2c_master_byte_ctrl.prj
...\i2c_master_byte_ctrl.stx
...\i2c_master_byte_ctrl.syr
...\i2c_master_byte_ctrl.v
...\i2c_master_byte_ctrl_vhdl.prj
...\i2c_master_defines.v
...\i2c_master_top.cmd_log
...\i2c_master_top.lso
...\i2c_master_top.ngc
...\i2c_master_top.ngr
...\i2c_master_top.prj
...\i2c_master_top.stx
...\i2c_master_top.syr
...\i2c_master_top.v
...\i2c_master_top_vhdl.prj
...\i2c_slave_model.fdo
...\i2c_slave_model.ndo
...\i2c_slave_model.udo
...\i2c_slave_model.v
...\prjname.lso
...\timescale.v
...\transcript
...\tst_bench_top.v
...\wb_master_model.v
...\__projnav.log
...\.........\coregen.rsp
...\.........\I2C.gfl
...\.........\I2C_flowplus.gfl
...\.........\i2c_master_bit_ctrl.xst
...\.........\i2c_master_byte_ctrl.xst
...\.........\i2c_master_top.xst
...\.........\runXst_tcl.rsp
...\.........\xst_sprjTOstx_tcl.rsp
...\xst\work\hdllib.ref
...\...\....\vlg67\i2c_master_top.bin
...\...\....\...5C\i2c_master_byte_ctrl.bin
...\...\....\...07\i2c_master_bit_ctrl.bin
...\work\_info
...\....\i2c_slave_model\verilog.asm
...\....\...............\_primary.dat
...\....\...............\_primary.vhd
...\....\glbl\verilog.asm
...\....\....\_primary.dat
...\....\....\_primary.vhd
...\xst\work\vlg67
...\...\....\vlg5C
...\...\....\vlg07
...\...\work
...\work\i2c_slave_model
...\....\glbl
...\__projnav
...\xst
...\work
I2C