文件名称:SDRAMcontrol

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [PDF]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1007kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 曾*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

用VHDL编写的SDRAM控制器,能实现SDRAM的读写控制及片选。-Prepared using VHDL SDRAM controller, able to SDRAM read and write control and chip select.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

doc

...\ddr_sdram.pdf

model

.....\mt46v4m16.vhd

.....\mti_pkg.vhd

readme.txt

route

.....\ddr_sdram.csf

.....\ddr_sdram.esf

.....\ddr_sdram.psf

.....\ddr_sdram.quartus

.....\ddr_sdram.vqm

.....\pll1.vhd

simulation

..........\APEX20KE_MF.VHD

..........\ddr_command.vhd

..........\ddr_control_interface.vhd

..........\ddr_data_path.vhd

..........\ddr_sdram.vhd

..........\ddr_sdram_tb.vhd

..........\io_utils.vhd

..........\lpm_pack.vhd

..........\modelsim.ini

..........\mt46v4m16.vhd

..........\mti_pkg.bak

..........\mti_pkg.vhd

..........\pll1.vhd

..........\readme.txt

..........\stdlogar.vhd

..........\util1164.vhd

..........\wave.do

..........\work

..........\....\altcam

..........\....\......\behave.dat

..........\....\......\behave.psm

..........\....\......\_primary.dat

..........\....\altclklock

..........\....\..........\behavior.dat

..........\....\..........\behavior.psm

..........\....\..........\_primary.dat

..........\....\altlvds_rx

..........\....\..........\behavior.dat

..........\....\..........\behavior.psm

..........\....\..........\_primary.dat

..........\....\altlvds_tx

..........\....\..........\behavior.dat

..........\....\..........\behavior.psm

..........\....\..........\_primary.dat

..........\....\command

..........\....\.......\rtl.dat

..........\....\.......\rtl.psm

..........\....\.......\_primary.dat

..........\....\control_interface

..........\....\.................\rtl.dat

..........\....\.................\rtl.psm

..........\....\.................\_primary.dat

..........\....\ddr_command

..........\....\...........\rtl.dat

..........\....\...........\rtl.psm

..........\....\...........\_primary.dat

..........\....\ddr_control_interface

..........\....\.....................\rtl.dat

..........\....\.....................\rtl.psm

..........\....\.....................\_primary.dat

..........\....\ddr_data_path

..........\....\.............\rtl.dat

..........\....\.............\rtl.psm

..........\....\.............\_primary.dat

..........\....\ddr_sdram

..........\....\.........\rtl.dat

..........\....\.........\rtl.psm

..........\....\.........\_primary.dat

..........\....\ddr_sdram_tb

..........\....\............\rtl.dat

..........\....\............\rtl.psm

..........\....\............\_primary.dat

..........\....\io_utils

..........\....\........\body.dat

..........\....\........\body.psm

..........\....\........\_primary.dat

..........\....\........\_vhdl.psm

..........\....\lpm_components

..........\....\..............\body.dat

..........\....\..............\body.psm

..........\....\..............\_primary.dat

..........\....\..............\_vhdl.psm

..........\....\mt46v4m16

..........\....\.........\behave.dat

..........\....\.........\behave.psm

..........\....\.........\_primary.dat

..........\....\mti_pkg

..........\....\.......\body.dat

..........\....\.......\body.psm

..........\....\.......\_primary.dat

..........\....\.......\_vhdl.psm

..........\....\pll1

..........\....\....\syn.dat

..........\....\....\syn.psm

..........\....\....\_primary.dat

..........\....\std_logic_arith

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