文件名称:XAPP868

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [PDF]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 764kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • ganz****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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E1/T1时钟提取和恢复源码 是xilinx的IP源码-E1/T1 clock recover code,it is xilinx s IP code
相关搜索: E1
E1
ip
Xapp868

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下载文件列表

XAPP868\flowcontrolpdf.doc

.......\readme.txt

.......\Verilog_version\code\cspro\icon.arg

.......\...............\....\.....\icon.edn

.......\...............\....\.....\icon.ncf

.......\...............\....\.....\icon_xst_example.v

.......\...............\....\.....\icon_xst_verilog_example.arg

.......\...............\....\.....\ml523.cpj

.......\...............\....\.....\vio.arg

.......\...............\....\.....\vio.cdc

.......\...............\....\.....\vio.edn

.......\...............\....\.....\vio.ncf

.......\...............\....\.....\vio_xst_example.v

.......\...............\....\.....\vio_xst_verilog_example.arg

.......\...............\....\datasampler.v

.......\...............\....\f_meter.v

.......\...............\....\IBUFGDS.v

.......\...............\....\icon_xst_example.v

.......\...............\....\lp_filter.v

.......\...............\....\modules_ngc\SPARTAN3A-3AN\lp_filter.ngc

.......\...............\....\...........\.............\vco.ngc

.......\...............\....\...........\V2P\lp_filter.ngc

.......\...............\....\...........\...\vco.ngc

.......\...............\....\...........\.4\lp_filter.ngc

.......\...............\....\...........\..\vco.ngc

.......\...............\....\...........\.5\lp_filter.ngc

.......\...............\....\...........\..\vco.ngc

.......\...............\....\ph_meter.v

.......\...............\....\prbschk.v

.......\...............\....\prbsgen.v

.......\...............\....\top_cdr.v

.......\...............\....\top_level.ucf

.......\...............\....\top_level.v

.......\...............\....\tran_detect.v

.......\...............\....\vco.v

.......\...............\testbenches\tb_cdr.v

.......\...............\...........\wave_set.do

.......\.HDL_version\code\cspro\icon.arg

.......\............\....\.....\icon.edn

.......\............\....\.....\icon.ncf

.......\............\....\.....\icon_xst_example.vhd

.......\............\....\.....\icon_xst_vhdl_example.arg

.......\............\....\.....\ml523.cpj

.......\............\....\.....\vio.arg

.......\............\....\.....\vio.cdc

.......\............\....\.....\vio.edn

.......\............\....\.....\vio.ncf

.......\............\....\.....\vio_xst_example.vhd

.......\............\....\.....\vio_xst_vhdl_example.arg

.......\............\....\datasampler.vhd

.......\............\....\Freq_meter.vhd

.......\............\....\modules_ngc\SPARTAN3A-3AN\lp_filter.ngc

.......\............\....\...........\.............\vco.ngc

.......\............\....\...........\V2P\lp_filter.ngc

.......\............\....\...........\...\vco.ngc

.......\............\....\...........\.4\lp_filter.ngc

.......\............\....\...........\..\vco.ngc

.......\............\....\...........\.5\lp_filter.ngc

.......\............\....\...........\..\vco.ngc

.......\............\....\phase_meter.vhd

.......\............\....\prbschk.vhd

.......\............\....\prbsgen.vhd

.......\............\....\top_cdr.vhd

.......\............\....\top_level.ucf

.......\............\....\top_level.vhd

.......\............\....\tran_detect.vhd

.......\............\testbenches\tb_cdr.vhd

.......\............\...........\wave_tb_cdr.do

.......\xapp868.pdf

.......\xapp868.zip

.......\Verilog_version\code\modules_ngc\SPARTAN3A-3AN

.......\...............\....\...........\V2P

.......\...............\....\...........\V4

.......\...............\....\...........\V5

.......\.HDL_version\code\modules_ngc\SPARTAN3A-3AN

.......\............\....\...........\V2P

.......\............\....\...........\V4

.......\............\....\...........\V5

.......\.erilog_version\code\cspro

.......\...............\....\modules_ngc

.......\.HDL_version\code\cspro

.......\............\....\modules_ngc

.......\.erilog_version\code

.......\...............\testbenches

.......\.HDL_version\code

.......\............\testbenches

.......\Verilog_version

.......\VHDL_version

XAPP868

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