文件名称:HW3

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [HTML]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 289kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • Xin***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

Write VHDL codes to model an 8-bit counter that counts every second. It counts from your last two digits of your student ID to your next two digits of your student ID. If the last two digits are greater than the next two digits, the counters counts down otherwise, it counts up. The counter should have asynchronous set input to set the count to your last two digits of your student ID, synchronous clear input to clear the count to 0, and enable input to enable counting. Set input has higher priority than the clear input. For now, you may assume that the clock to the counter is a 1 Hz clock. For subsequent homework, you need to design a circuit that generates the 1 Hz clock signal from the 50 MHz system clock.-Count starts from 78 down to 56, back to 78, counts down to 56, and repeat. If the counter is cleared, count starts from 0 up to 78 and then counts down to 56, back to 78, and repeat. If the counter is set, the count sets to 78. The counter will not count when it is disabled. 
相关搜索: counter
verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

HW3\db\HW3.asm.qmsg

...\..\HW3.asm.rdb

...\..\HW3.asm_labs.ddb

...\..\HW3.cbx.xml

...\..\HW3.cmp.bpm

...\..\HW3.cmp.cdb

...\..\HW3.cmp.ecobp

...\..\HW3.cmp.hdb

...\..\HW3.cmp.kpt

...\..\HW3.cmp.logdb

...\..\HW3.cmp.rdb

...\..\HW3.cmp.tdb

...\..\HW3.cmp0.ddb

...\..\HW3.cmp_merge.kpt

...\..\HW3.db_info

...\..\HW3.eco.cdb

...\..\HW3.eds_overflow

...\..\HW3.fit.qmsg

...\..\HW3.fnsim.cdb

...\..\HW3.fnsim.hdb

...\..\HW3.fnsim.qmsg

...\..\HW3.hier_info

...\..\HW3.hif

...\..\HW3.lpc.html

...\..\HW3.lpc.rdb

...\..\HW3.lpc.txt

...\..\HW3.map.bpm

...\..\HW3.map.cdb

...\..\HW3.map.ecobp

...\..\HW3.map.hdb

...\..\HW3.map.kpt

...\..\HW3.map.logdb

...\..\HW3.map.qmsg

...\..\HW3.map_bb.cdb

...\..\HW3.map_bb.hdb

...\..\HW3.map_bb.logdb

...\..\HW3.pre_map.cdb

...\..\HW3.pre_map.hdb

...\..\HW3.rtlv.hdb

...\..\HW3.rtlv_sg.cdb

...\..\HW3.rtlv_sg_swap.cdb

...\..\HW3.sgdiff.cdb

...\..\HW3.sgdiff.hdb

...\..\HW3.sim.hdb

...\..\HW3.sim.qmsg

...\..\HW3.sim.rdb

...\..\HW3.simfam

...\..\HW3.sim_ori.vwf

...\..\HW3.sld_design_entry.sci

...\..\HW3.sld_design_entry_dsc.sci

...\..\HW3.smart_action.txt

...\..\HW3.syn_hier_info

...\..\HW3.tan.qmsg

...\..\HW3.tis_db_list.ddb

...\..\logic_util_heursitic.dat

...\..\prev_cmp_HW3.asm.qmsg

...\..\prev_cmp_HW3.fit.qmsg

...\..\prev_cmp_HW3.map.qmsg

...\..\prev_cmp_HW3.qmsg

...\..\prev_cmp_HW3.tan.qmsg

...\..\wed.wsf

...\HW3.asm.rpt

...\HW3.done

...\HW3.fit.rpt

...\HW3.fit.summary

...\HW3.flow.rpt

...\HW3.map.rpt

...\HW3.map.summary

...\HW3.pin

...\HW3.pof

...\HW3.qpf

...\HW3.qsf

...\HW3.qws

...\HW3.sim.rpt

...\HW3.sof

...\HW3.tan.rpt

...\HW3.tan.summary

...\HW3.vhd

...\HW3.vhd.bak

...\HW3.vwf

...\incremental_db\compiled_partitions\HW3.root_partition.cmp.cdb

...\..............\...................\HW3.root_partition.cmp.dfp

...\..............\...................\HW3.root_partition.cmp.hdb

...\..............\...................\HW3.root_partition.cmp.kpt

...\..............\...................\HW3.root_partition.cmp.logdb

...\..............\...................\HW3.root_partition.cmp.rcfdb

...\..............\...................\HW3.root_partition.cmp.re.rcfdb

...\..............\...................\HW3.root_partition.map.cdb

...\..............\...................\HW3.root_partition.map.dpi

...\..............\...................\HW3.root_partition.map.hdb

...\..............\...................\HW3.root_partition.map.kpt

...\..............\README

...\Waveform1.vwf

...\incremental_db\compiled_partitions

...\db

...\incremental_db

HW3

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