文件名称:CLOCK-ON-ALTERA-DEV-NOARD-RONTEX

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
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  • 972kb
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  • needtob*******
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这是我上电子线路设计课程时自己写的数字钟设计的整个工程.网上下载安装quartus II软件后双击clock.sof打开调试.若软件说没有权限,请删除db文件夹后再试.

文件夹中附带我的实验报告,其中详细讲解了我的设计思路\软件架构\可能出现的问题等等.

调试步骤就不讲了,管脚分配请网友自行完成.

开发板 Altera Cyclone II EP2C35F672C6

软件平台 Quartus II

语言 verilogHDL-These are all the project files and source codes of a digital clock designed on the ALTERA dev. board using Quartus II in verilogHDL when I was taking the electronics design course.

The basic functions are realized here and more details are explained in the attached experiment report. If there are any problems with the codes or debugging, please contact me at zhouyicheng1990@126.com.



Develop Board:

Altera Cyclone II EP2C35F672C6

Software:

Quartus II

Language:

verilogHDL
相关搜索: 数字钟
VHDL

(系统自动生成,下载前可以参看下载内容)

下载文件列表

CLOCK ON ALTERA DEV NOARD-RONTEX\zhou[01c60][0616]\ActState.bsf

................................\.................\ActState.v

................................\.................\Alarm.bsf

................................\.................\Alarm.v

................................\.................\AlarmState.bsf

................................\.................\AlarmState.v

................................\.................\AlarmState.v.bak

................................\.................\clock.asm.rpt

................................\.................\clock.bdf

................................\.................\clock.cdf

................................\.................\clock.done

................................\.................\clock.dpf

................................\.................\clock.fit.rpt

................................\.................\clock.fit.smsg

................................\.................\clock.fit.summary

................................\.................\clock.flow.rpt

................................\.................\clock.map.rpt

................................\.................\clock.map.smsg

................................\.................\clock.map.summary

................................\.................\clock.pin

................................\.................\clock.pof

................................\.................\clock.qpf

................................\.................\clock.qsf

................................\.................\clock.qws

................................\.................\clock.sof

................................\.................\clock.tan.rpt

................................\.................\clock.tan.summary

................................\.................\ClockMainCntrl.bsf

................................\.................\ClockMainCntrl.v

................................\.................\ClockMainCntrl.v.bak

................................\.................\Counter10.bsf

................................\.................\Counter10.v

................................\.................\Counter24.bsf

................................\.................\Counter24.v

................................\.................\Counter24.v.bak

................................\.................\Counter6.bsf

................................\.................\Counter6.v

................................\.................\Counter60.bsf

................................\.................\Counter60.v

................................\.................\Counter60.v.bak

................................\.................\db\clock.asm.qmsg

................................\.................\..\clock.asm_labs.ddb

................................\.................\..\clock.cbx.xml

................................\.................\..\clock.cmp.bpm

................................\.................\..\clock.cmp.cdb

................................\.................\..\clock.cmp.ecobp

................................\.................\..\clock.cmp.hdb

................................\.................\..\clock.cmp.logdb

................................\.................\..\clock.cmp.rdb

................................\.................\..\clock.cmp.tdb

................................\.................\..\clock.cmp0.ddb

................................\.................\..\clock.cmp_bb.cdb

................................\.................\..\clock.cmp_bb.hdb

................................\.................\..\clock.cmp_bb.logdb

................................\.................\..\clock.cmp_bb.rcf

................................\.................\..\clock.dbp

................................\.................\..\clock.db_info

................................\.................\..\clock.eco.cdb

................................\.................\..\clock.fit.qmsg

................................\.................\..\clock.hier_info

................................\.................\..\clock.hif

................................\.................\..\clock.map.bpm

......

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