文件名称:Fre_Counter_verilog

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.09mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • yun***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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基于ep3c25的FPGA频率计的简单设计(用verilog HDL),直接打开即可-FPGA frequency counter based on ep3c25 of simple design (using verilog HDL), can directly open the ... ...
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Fre_Counter_verilog\db\cntr_88i.tdf

...................\..\Fre_Counter_verilog.asm.qmsg

...................\..\Fre_Counter_verilog.cbx.xml

...................\..\Fre_Counter_verilog.cmp.ecobp

...................\..\Fre_Counter_verilog.cmp.rdb

...................\..\Fre_Counter_verilog.cmp_bb.cdb

...................\..\Fre_Counter_verilog.cmp_bb.hdb

...................\..\Fre_Counter_verilog.cmp_bb.logdb

...................\..\Fre_Counter_verilog.cmp_bb.rcf

...................\..\Fre_Counter_verilog.cuda_io_sim_cache.ff_0.hsd

...................\..\Fre_Counter_verilog.cuda_io_sim_cache.ss_85.hsd

...................\..\Fre_Counter_verilog.dbp

...................\..\Fre_Counter_verilog.db_info

...................\..\Fre_Counter_verilog.eco.cdb

...................\..\Fre_Counter_verilog.eds_overflow

...................\..\Fre_Counter_verilog.fit.qmsg

...................\..\Fre_Counter_verilog.fnsim.cdb

...................\..\Fre_Counter_verilog.fnsim.hdb

...................\..\Fre_Counter_verilog.fnsim.qmsg

...................\..\Fre_Counter_verilog.hier_info

...................\..\Fre_Counter_verilog.hif

...................\..\Fre_Counter_verilog.map.bpm

...................\..\Fre_Counter_verilog.map.cdb

...................\..\Fre_Counter_verilog.map.ecobp

...................\..\Fre_Counter_verilog.map.hdb

...................\..\Fre_Counter_verilog.map.logdb

...................\..\Fre_Counter_verilog.map.qmsg

...................\..\Fre_Counter_verilog.map_bb.cdb

...................\..\Fre_Counter_verilog.map_bb.hdb

...................\..\Fre_Counter_verilog.map_bb.logdb

...................\..\Fre_Counter_verilog.pre_map.cdb

...................\..\Fre_Counter_verilog.pre_map.hdb

...................\..\Fre_Counter_verilog.psp

...................\..\Fre_Counter_verilog.pss

...................\..\Fre_Counter_verilog.rtlv.hdb

...................\..\Fre_Counter_verilog.rtlv_sg.cdb

...................\..\Fre_Counter_verilog.rtlv_sg_swap.cdb

...................\..\Fre_Counter_verilog.sgdiff.cdb

...................\..\Fre_Counter_verilog.sgdiff.hdb

...................\..\Fre_Counter_verilog.sim.cvwf

...................\..\Fre_Counter_verilog.sim.hdb

...................\..\Fre_Counter_verilog.sim.qmsg

...................\..\Fre_Counter_verilog.sim.rdb

...................\..\Fre_Counter_verilog.simfam

...................\..\Fre_Counter_verilog.sld_design_entry.sci

...................\..\Fre_Counter_verilog.sld_design_entry_dsc.sci

...................\..\Fre_Counter_verilog.sta.qmsg

...................\..\Fre_Counter_verilog.sta.rdb

...................\..\Fre_Counter_verilog.syn_hier_info

...................\..\Fre_Counter_verilog.tiscmp.fast_1200mv_0c.ddb

...................\..\Fre_Counter_verilog.tiscmp.slow_1200mv_0c.ddb

...................\..\Fre_Counter_verilog.tiscmp.slow_1200mv_85c.ddb

...................\..\Fre_Counter_verilog.tis_db_list.ddb

...................\..\mux_7qc.tdf

...................\..\prev_cmp_Fre_Counter_verilog.asm.qmsg

...................\..\prev_cmp_Fre_Counter_verilog.fit.qmsg

...................\..\prev_cmp_Fre_Counter_verilog.map.qmsg

...................\..\prev_cmp_Fre_Counter_verilog.qmsg

...................\..\prev_cmp_Fre_Counter_verilog.sim.qmsg

...................\..\prev_cmp_Fre_Counter_verilog.sta.qmsg

...................\..\wed.wsf

...................\Fre_Counter_verilog.asm.rpt

...................\Fre_Counter_verilog.bdf

...................\Fre_Counter_verilog.done

...................\Fre_Counter_verilog.dpf

...................\Fre_Counter_verilog.fit.rpt

...................\Fre_Counter_verilog.fit.smsg

...................\Fre_Counter_verilog.fit.summary

...................\Fre_Counter_verilog.flow.rpt

...................\Fre_Counter_verilog.map.rpt

...................\Fre_Counter_verilog.map.smsg

...................\Fre_Counter_verilog.map.summary

...................\Fre_Counter_verilog.pin

...................\Fre_Counter_verilog.pof

...................\Fre_Counter_verilog.qpf

...................\Fre_Counter_verilog.qsf

...................\Fre_Counter_verilog.qws

...................\Fre_Counter_

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