文件名称:fir_data_ram_FPGA

  • 所属分类:
  • matlab例程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 378kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 陈*
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采用FPGA工具实现的无线脉冲响应滤波器-Implemented using FPGA tools wireless impulse response filter
(系统自动生成,下载前可以参看下载内容)

下载文件列表

fir_data_ram_FPGA\fir_data_ram\data_ram.asy

.................\............\data_ram.edn

.................\............\data_ram.ngo

.................\............\data_ram.sym

.................\............\data_ram.v

.................\............\data_ram.veo

.................\............\data_ram.vhd

.................\............\data_ram.vho

.................\............\data_ram.xco

.................\............\data_ram_flist.txt

.................\............\data_ram_readme.txt

.................\............\fir_data_ram.cmd_log

.................\............\fir_data_ram.ise

.................\............\fir_data_ram.ise_ISE_Backup

.................\............\fir_data_ram.lso

.................\............\fir_data_ram.ngc

.................\............\fir_data_ram.ngr

.................\............\fir_data_ram.ntrc_log

.................\............\fir_data_ram.prj

.................\............\fir_data_ram.stx

.................\............\fir_data_ram.syr

.................\............\fir_data_ram.vhd

.................\............\fir_data_ram.xst

.................\............\fir_data_ram_tb.vhd

.................\............\fir_data_ram_tb_vhd.fdo

.................\............\fir_data_ram_tb_vhd.udo

.................\............\pepExtractor.prj

.................\............\templates\coregen.xml

.................\............\transcript

.................\............\vsim.wlf

.................\............\work\data_ram\verilog.asm

.................\............\....\........\_primary.dat

.................\............\....\........\_primary.vhd

.................\............\....\fir_data_ram\behavioral.asm

.................\............\....\............\behavioral.dat

.................\............\....\............\_primary.dat

.................\............\....\............_tb_vhd\behavior.asm

.................\............\....\...................\behavior.dat

.................\............\....\...................\_primary.dat

.................\............\....\glbl\verilog.asm

.................\............\....\....\_primary.dat

.................\............\....\....\_primary.vhd

.................\............\....\_info

.................\............\xst\dump.xst\fir_data_ram.prj\ntrc.scr

.................\............\...\work\hdllib.ref

.................\............\...\....\hdpdeps.ref

.................\............\...\....\sub00\vhpl00.vho

.................\............\...\....\.....\vhpl01.vho

.................\............\...\....\vlg29\data__ram.bin

.................\............\_xmsgs\xst.xmsgs

.................\............\xst\dump.xst\fir_data_ram.prj\ngx\notopt

.................\............\...\........\................\...\opt

.................\............\...\........\................\ngx

.................\............\...\........\fir_data_ram.prj

.................\............\...\work\sub00

.................\............\...\....\vlg29

.................\............\work\data_ram

.................\............\....\fir_data_ram

.................\............\....\fir_data_ram_tb_vhd

.................\............\....\glbl

.................\............\xst\dump.xst

.................\............\...\projnav.tmp

.................\............\...\work

.................\............\templates

.................\............\work

.................\............\xst

.................\............\_cg

.................\............\_xmsgs

.................\fir_data_ram

fir_data_ram_FPGA

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