文件名称:compare

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [Windows] [程序]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 123kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • l***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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一个用verilog写的基本的比较器,其中带了一些其他的电路,也是用verilog编的,希望对读者有用。-Use verilog to write a basic comparator, which brought a number of other circuits, but also with the verilog code, and I hope useful to readers.
相关搜索: verilog
compare

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下载文件列表

compare\compare.cmd_log

.......\compare.gise

.......\compare.ise

.......\compare.lso

.......\compare.ngc

.......\compare.ngr

.......\compare.prj

.......\compare.stx

.......\compare.syr

.......\compare.v

.......\compare.xise

.......\compare.xst

.......\compare_beh.prj

.......\compare_isim_beh.exe

.......\compare_isim_beh.wdb

.......\compare_summary.html

.......\........xdb\tmp\ise\version

.......\...........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject

.......\...........\...\...\............\..................\.........\HDProject_StrTbl

.......\...........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl

.......\...........\...\...\............\.........\.......\RunOnce_tcl_StrTbl

.......\...........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main

.......\...........\...\...\............\................\................\dpm_project_main_StrTbl

.......\...........\...\...\............\................Gui\CSourceProcessView

.......\...........\...\...\............\...................\CSourceProcessView_StrTbl

.......\...........\...\...\............\...................\CViewSelector

.......\...........\...\...\............\...................\CViewSelector_StrTbl

.......\...........\...\...\............\...................\File-SynthesisOnly

.......\...........\...\...\............\...................\File-SynthesisOnly_StrTbl

.......\...........\...\...\............\...................\Library-SynthesisOnly

.......\...........\...\...\............\...................\Library-SynthesisOnly_StrTbl

.......\...........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG

.......\...........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG_StrTbl

.......\...........\...\...\............\...................\Process-SynthesisOnly-

.......\...........\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG

.......\...........\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG_StrTbl

.......\...........\...\...\............\...................\Process-SynthesisOnly-_StrTbl

.......\...........\...\...\............\...................\Source-BehavioralSim-AutoCompile

.......\...........\...\...\............\...................\Source-BehavioralSim-AutoCompile_StrTbl

.......\...........\...\...\............\...................\Source-SynthesisOnly-AutoCompile

.......\...........\...\...\............\...................\Source-SynthesisOnly-AutoCompile_StrTbl

.......\...........\...\...\............\xreport\Gc_RvReportViewer-Current-Module

.......\...........\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl

.......\...........\...\...\............\.......\Gc_RvReportViewer-Module-Data-compare

.......\...........\...\...\............\.......\Gc_RvReportViewer-Module-Data-compare_StrTbl

.......\...........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default

.......\...........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl

.......\...........\...\...\..REGISTRY__\Autonym\regkeys

.......\...........\...\...\............\bitgen\regkeys

.......\...........\...\...\............\...init\regkeys

.......\...........\...\...\............\common\regkeys

.......\...........\...\...\............\.pldfit\regkeys

.......\...........\...\...\............\dumpngdio\regkeys

.......\...........\...\...\............\fuse\regkeys

.......\...........\...\...\............\HierarchicalDesign\HDProject\regkeys

.......\...........\...\...\............\..................\regkeys

.......\...........\...\...\............\hprep6\regkeys

.......\...........\...\...\............\idem\regkeys

.......\...........\...\...\............\libgen\regkeys

.......\...........\...\...\............\map\regkeys

.......\...........\...\...\............\netgen\regkeys

.......\...........\...\...\............\.gc2edif\regkeys

.......\...........\...\...\............\...build\regkeys

.......\...........\...\...\............\..dbuild\regkeys

.......\...........\...\...\.

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