文件名称:KD-CPU
介绍说明－－下载内容均来自于网络，请自行研究使用
计算机原理课程设计给予Verilog做的课题，丰富的指令支持，LOOP，TRAP、以及子程序调用等-Principles of curriculum design to do the computer issues a rich instruction support, LOOP, TRAP, and subroutine calls, etc.
相关搜索： cpu
(系统自动生成,下载前可以参看下载内容)
下载文件列表
KD-CPU\.untf
......\ALU.bld
......\ALU.cmd_log
......\ALU.lso
......\ALU.mrp
......\ALU.nc1
......\ALU.ngc
......\ALU.ngd
......\ALU.ngm
......\ALU.ngr
......\ALU.pcf
......\ALU.prj
......\ALU.spl
......\ALU.stx
......\ALU.sym
......\ALU.syr
......\ALU.v
......\ALU.v.bak
......\ALU_map.ncd
......\ALU_map.ngm
......\ALU_summary.html
......\alu_top.v
......\alu_top.v.bak
......\alu_top_summary.html
......\alu_vhdl.prj
......\automake.log
......\clock.cmd_log
......\clock.lso
......\clock.ngr
......\clock.prj
......\clock.stx
......\clock.syr
......\clock.v
......\clock.v.bak
......\clock_summary.html
......\clock_vhdl.prj
......\CONSEAL.cmd_log
......\CONSEAL.lso
......\CONSEAL.ngr
......\CONSEAL.prj
......\CONSEAL.sch
......\CONSEAL.stx
......\CONSEAL.syr
......\CONSEAL.v
......\CONSEAL.vf
......\CONSEAL_summary.html
......\conseal_vhdl.prj
......\con_top.v
......\CPU.cmd_log
......\CPU.lso
......\CPU.ngr
......\CPU.prj
......\CPU.syr
......\CPU_summary.html
......\cpu_vhdl.prj
......\CU.cmd_log
......\CU.lso
......\CU.ngr
......\CU.prj
......\CU.stx
......\CU.syr
......\CU.v
......\CU.v.bak
......\CU_summary.html
......\cu_vhdl.prj
......\CX.cmd_log
......\CX.lso
......\CX.ngr
......\CX.prj
......\CX.stx
......\CX.syr
......\CX.v
......\CX_summary.html
......\cx_vhdl.prj
......\GR.bld
......\GR.cmd_log
......\GR.lso
......\GR.ngc
......\GR.ngd
......\GR.ngr
......\GR.prj
......\GR.stx
......\GR.syr
......\GR.v
......\GR.v.bak
......\GR_summary.html
......\gr_top.v
......\gr_top.v.bak
......\gr_vhdl.prj
......\INT_MAIN.cmd_log
......\INT_MAIN.lso
......\INT_MAIN.ngr
......\INT_MAIN.prj
......\INT_MAIN.stx
......\INT_MAIN.syr
......\INT_MAIN.v
......\INT_MAIN_summary.html
......\int_main_vhdl.prj
......\INT_TOP.v
......\INT_VEC.cmd_log
......\ALU.bld
......\ALU.cmd_log
......\ALU.lso
......\ALU.mrp
......\ALU.nc1
......\ALU.ngc
......\ALU.ngd
......\ALU.ngm
......\ALU.ngr
......\ALU.pcf
......\ALU.prj
......\ALU.spl
......\ALU.stx
......\ALU.sym
......\ALU.syr
......\ALU.v
......\ALU.v.bak
......\ALU_map.ncd
......\ALU_map.ngm
......\ALU_summary.html
......\alu_top.v
......\alu_top.v.bak
......\alu_top_summary.html
......\alu_vhdl.prj
......\automake.log
......\clock.cmd_log
......\clock.lso
......\clock.ngr
......\clock.prj
......\clock.stx
......\clock.syr
......\clock.v
......\clock.v.bak
......\clock_summary.html
......\clock_vhdl.prj
......\CONSEAL.cmd_log
......\CONSEAL.lso
......\CONSEAL.ngr
......\CONSEAL.prj
......\CONSEAL.sch
......\CONSEAL.stx
......\CONSEAL.syr
......\CONSEAL.v
......\CONSEAL.vf
......\CONSEAL_summary.html
......\conseal_vhdl.prj
......\con_top.v
......\CPU.cmd_log
......\CPU.lso
......\CPU.ngr
......\CPU.prj
......\CPU.syr
......\CPU_summary.html
......\cpu_vhdl.prj
......\CU.cmd_log
......\CU.lso
......\CU.ngr
......\CU.prj
......\CU.stx
......\CU.syr
......\CU.v
......\CU.v.bak
......\CU_summary.html
......\cu_vhdl.prj
......\CX.cmd_log
......\CX.lso
......\CX.ngr
......\CX.prj
......\CX.stx
......\CX.syr
......\CX.v
......\CX_summary.html
......\cx_vhdl.prj
......\GR.bld
......\GR.cmd_log
......\GR.lso
......\GR.ngc
......\GR.ngd
......\GR.ngr
......\GR.prj
......\GR.stx
......\GR.syr
......\GR.v
......\GR.v.bak
......\GR_summary.html
......\gr_top.v
......\gr_top.v.bak
......\gr_vhdl.prj
......\INT_MAIN.cmd_log
......\INT_MAIN.lso
......\INT_MAIN.ngr
......\INT_MAIN.prj
......\INT_MAIN.stx
......\INT_MAIN.syr
......\INT_MAIN.v
......\INT_MAIN_summary.html
......\int_main_vhdl.prj
......\INT_TOP.v
......\INT_VEC.cmd_log