文件名称:VGA
介绍说明－－下载内容均来自于网络，请自行研究使用
VERILOG编写的VGA实验例程，包括整个工程，可以直接使用-VERILOG VGA written test routines, including the whole project, can be used directly
(系统自动生成,下载前可以参看下载内容)
下载文件列表
VGA实验\Project\VGA\constraint\vgatest.pdc
.......\.......\...\..........\vgatest_1.pdc
.......\.......\...\designer\impl1\designer.log
.......\.......\...\........\.....\designer_genhdl.log
.......\.......\...\........\.....\vgatest.adb
.......\.......\...\........\.....\........dtf\verify.log
.......\.......\...\........\.....\vgatest.ide_des
.......\.......\...\........\.....\vgatest.pdb
.......\.......\...\........\.....\vgatest.pdb.depends
.......\.......\...\........\.....\vgatest.tcl
.......\.......\...\........\.....\vgatest_ba.sdf
.......\.......\...\........\.....\vgatest_ba.v
.......\.......\...\........\.....\........fp\$$FlashPro_02165.L$$
.......\.......\...\........\.....\..........\$$FlashPro_FPBBALTLPT1.L$$
.......\.......\...\........\.....\..........\projectData\vgatest.pdb
.......\.......\...\........\.....\..........\vgatest.log
.......\.......\...\........\.....\..........\vgatest.pro
.......\.......\...\hdl\hdlsynchk.tcl
.......\.......\...\...\vgatest.v
.......\.......\...\simulation\meminit.dat
.......\.......\...\..........\modelsim.ini
.......\.......\...\..........\modelsim.ini.sav
.......\.......\...\.martgen\smartgen.aws
.......\.......\...\.ynthesis\.recordref
.......\.......\...\.........\stdout.log
.......\.......\...\.........\.yntmp\sap.log
.......\.......\...\.........\......\vgatest.msg
.......\.......\...\.........\......\vgatest.plg
.......\.......\...\.........\......\vgatest_flink.htm
.......\.......\...\.........\......\vgatest_srr.htm
.......\.......\...\.........\......\vgatest_toc.htm
.......\.......\...\.........\traplog.tlg
.......\.......\...\.........\vgatest.areasrr
.......\.......\...\.........\vgatest.edn
.......\.......\...\.........\vgatest.fse
.......\.......\...\.........\vgatest.htm
.......\.......\...\.........\vgatest.map
.......\.......\...\.........\vgatest.sap
.......\.......\...\.........\vgatest.sdf
.......\.......\...\.........\vgatest.srd
.......\.......\...\.........\vgatest.srm
.......\.......\...\.........\vgatest.srr
.......\.......\...\.........\vgatest.srs
.......\.......\...\.........\vgatest.tlg
.......\.......\...\.........\vgatest_drc.rpt
.......\.......\...\.........\vgatest_sdc.sdc
.......\.......\...\.........\vgatest_syn.prd
.......\.......\...\.........\vgatest_syn.prj
.......\.......\...\VGA.prj
.......\.......\...\viewdraw\vf\project.lst
.......\.......\...\........\viewdraw.ini
.......\Source\vgatest.v
.......\Project\VGA\designer\impl1\vgatest_fp\projectData
.......\.......\...\........\.....\simulation
.......\.......\...\........\.....\vgatest.dtf
.......\.......\...\........\.....\vgatest_fp
.......\.......\...\........\impl1
.......\.......\...\synthesis\syntmp
.......\.......\...\viewdraw\sch
.......\.......\...\........\sym
.......\.......\...\........\vf
.......\.......\...\........\wir
.......\.......\...\component
.......\.......\...\constraint
.......\.......\...\coreconsole
.......\.......\...\designer
.......\.......\...\hdl
.......\.......\...\phy_synthesis
.......\.......\...\simulation
.......\.......\...\smartgen
.......\.......\...\stimulus
.......\.......\...\synthesis
.......\.......\...\viewdraw
.......\.......\VGA
.......\Project
.......\Source
VGA实验
.......\.......\...\..........\vgatest_1.pdc
.......\.......\...\designer\impl1\designer.log
.......\.......\...\........\.....\designer_genhdl.log
.......\.......\...\........\.....\vgatest.adb
.......\.......\...\........\.....\........dtf\verify.log
.......\.......\...\........\.....\vgatest.ide_des
.......\.......\...\........\.....\vgatest.pdb
.......\.......\...\........\.....\vgatest.pdb.depends
.......\.......\...\........\.....\vgatest.tcl
.......\.......\...\........\.....\vgatest_ba.sdf
.......\.......\...\........\.....\vgatest_ba.v
.......\.......\...\........\.....\........fp\$$FlashPro_02165.L$$
.......\.......\...\........\.....\..........\$$FlashPro_FPBBALTLPT1.L$$
.......\.......\...\........\.....\..........\projectData\vgatest.pdb
.......\.......\...\........\.....\..........\vgatest.log
.......\.......\...\........\.....\..........\vgatest.pro
.......\.......\...\hdl\hdlsynchk.tcl
.......\.......\...\...\vgatest.v
.......\.......\...\simulation\meminit.dat
.......\.......\...\..........\modelsim.ini
.......\.......\...\..........\modelsim.ini.sav
.......\.......\...\.martgen\smartgen.aws
.......\.......\...\.ynthesis\.recordref
.......\.......\...\.........\stdout.log
.......\.......\...\.........\.yntmp\sap.log
.......\.......\...\.........\......\vgatest.msg
.......\.......\...\.........\......\vgatest.plg
.......\.......\...\.........\......\vgatest_flink.htm
.......\.......\...\.........\......\vgatest_srr.htm
.......\.......\...\.........\......\vgatest_toc.htm
.......\.......\...\.........\traplog.tlg
.......\.......\...\.........\vgatest.areasrr
.......\.......\...\.........\vgatest.edn
.......\.......\...\.........\vgatest.fse
.......\.......\...\.........\vgatest.htm
.......\.......\...\.........\vgatest.map
.......\.......\...\.........\vgatest.sap
.......\.......\...\.........\vgatest.sdf
.......\.......\...\.........\vgatest.srd
.......\.......\...\.........\vgatest.srm
.......\.......\...\.........\vgatest.srr
.......\.......\...\.........\vgatest.srs
.......\.......\...\.........\vgatest.tlg
.......\.......\...\.........\vgatest_drc.rpt
.......\.......\...\.........\vgatest_sdc.sdc
.......\.......\...\.........\vgatest_syn.prd
.......\.......\...\.........\vgatest_syn.prj
.......\.......\...\VGA.prj
.......\.......\...\viewdraw\vf\project.lst
.......\.......\...\........\viewdraw.ini
.......\Source\vgatest.v
.......\Project\VGA\designer\impl1\vgatest_fp\projectData
.......\.......\...\........\.....\simulation
.......\.......\...\........\.....\vgatest.dtf
.......\.......\...\........\.....\vgatest_fp
.......\.......\...\........\impl1
.......\.......\...\synthesis\syntmp
.......\.......\...\viewdraw\sch
.......\.......\...\........\sym
.......\.......\...\........\vf
.......\.......\...\........\wir
.......\.......\...\component
.......\.......\...\constraint
.......\.......\...\coreconsole
.......\.......\...\designer
.......\.......\...\hdl
.......\.......\...\phy_synthesis
.......\.......\...\simulation
.......\.......\...\smartgen
.......\.......\...\stimulus
.......\.......\...\synthesis
.......\.......\...\viewdraw
.......\.......\VGA
.......\Project
.......\Source
VGA实验