文件名称:FIFO
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基于FPGA的FIFO控制器的设计与实现，ISE，verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
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下载文件列表
FIFO\fifo.cr.mti
....\fifo.mpf
....\generic_fifo_sc.v
....\note.txt
....\test_bench_top.v
....\timescale.v
....\transcript
....\work\_info
....\....\test_bench_top\verilog.asm
....\....\..............\_primary.dat
....\....\..............\_primary.vhd
....\....\lfsr\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\generic_fifo_sc_a\verilog.asm
....\....\.................\_primary.dat
....\....\.................\_primary.vhd
....\....\...............\verilog.asm
....\....\...............\_primary.dat
....\....\...............\_primary.vhd
....\....\.............lfsr\verilog.asm
....\....\.................\_primary.dat
....\....\.................\_primary.vhd
....\....\.............dc_gray\verilog.asm
....\....\....................\_primary.dat
....\....\....................\_primary.vhd
....\....\...............\verilog.asm
....\....\...............\_primary.dat
....\....\...............\_primary.vhd
....\....\........dpram\verilog.asm
....\....\.............\_primary.dat
....\....\.............\_primary.vhd
....\chart\图9-10.bmp
....\.....\图9-4.bmp
....\.....\图9-5.bmp
....\.....\图9-6.bmp
....\.....\图9-9.bmp
....\work\test_bench_top
....\....\lfsr
....\....\generic_fifo_sc_a
....\....\generic_fifo_sc
....\....\generic_fifo_lfsr
....\....\generic_fifo_dc_gray
....\....\generic_fifo_dc
....\....\generic_dpram
....\work
....\chart
FIFO
....\fifo.mpf
....\generic_fifo_sc.v
....\note.txt
....\test_bench_top.v
....\timescale.v
....\transcript
....\work\_info
....\....\test_bench_top\verilog.asm
....\....\..............\_primary.dat
....\....\..............\_primary.vhd
....\....\lfsr\verilog.asm
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\generic_fifo_sc_a\verilog.asm
....\....\.................\_primary.dat
....\....\.................\_primary.vhd
....\....\...............\verilog.asm
....\....\...............\_primary.dat
....\....\...............\_primary.vhd
....\....\.............lfsr\verilog.asm
....\....\.................\_primary.dat
....\....\.................\_primary.vhd
....\....\.............dc_gray\verilog.asm
....\....\....................\_primary.dat
....\....\....................\_primary.vhd
....\....\...............\verilog.asm
....\....\...............\_primary.dat
....\....\...............\_primary.vhd
....\....\........dpram\verilog.asm
....\....\.............\_primary.dat
....\....\.............\_primary.vhd
....\chart\图9-10.bmp
....\.....\图9-4.bmp
....\.....\图9-5.bmp
....\.....\图9-6.bmp
....\.....\图9-9.bmp
....\work\test_bench_top
....\....\lfsr
....\....\generic_fifo_sc_a
....\....\generic_fifo_sc
....\....\generic_fifo_lfsr
....\....\generic_fifo_dc_gray
....\....\generic_fifo_dc
....\....\generic_dpram
....\work
....\chart
FIFO