文件名称:sobel
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Verilog代码实现Sobel算子，包括整个工程，仿真也有。。仿真表明该程序能实现Sobel 算子硬件实现-Verilog，Sobel Operator
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下载文件列表
sobel\adder_subtracter_virtex4_7_0_159cd80bedeb8dd7.edn
.....\adder_subtracter_virtex4_7_0_159cd80bedeb8dd7.ngo
.....\adder_subtracter_virtex4_7_0_a05976c5f0c94e14.edn
.....\adder_subtracter_virtex4_7_0_a05976c5f0c94e14.ngo
.....\adder_subtracter_virtex4_7_0_ca4e72d019e5d592.edn
.....\adder_subtracter_virtex4_7_0_ca4e72d019e5d592.ngo
.....\adder_subtracter_virtex4_7_0_f0f86c7ab6cab538.edn
.....\adder_subtracter_virtex4_7_0_f0f86c7ab6cab538.ngo
.....\binary_counter_virtex4_7_0_8c95a38a32cd3add.edn
.....\binary_counter_virtex4_7_0_8c95a38a32cd3add.ngo
.....\bmg_24_vx4_e54e5a776fc5110c.mif
.....\bmg_24_vx4_e54e5a776fc5110c.ngc
.....\globals
.....\hdlFiles
.....\modelsim\sobel\adder_subtracter_virtex4_7_0_159cd80bedeb8dd7\verilog.asm
.....\........\.....\.............................................\verilog.rw
.....\........\.....\.............................................\_primary.dat
.....\........\.....\.............................................\_primary.dbs
.....\........\.....\.............................................\_primary.vhd
.....\........\.....\adder_subtracter_virtex4_7_0_159cd80bedeb8dd7
.....\........\.....\.............................a05976c5f0c94e14\verilog.asm
.....\........\.....\.............................................\verilog.rw
.....\........\.....\.............................................\_primary.dat
.....\........\.....\.............................................\_primary.dbs
.....\........\.....\.............................................\_primary.vhd
.....\........\.....\adder_subtracter_virtex4_7_0_a05976c5f0c94e14
.....\........\.....\.............................ca4e72d019e5d592\verilog.asm
.....\........\.....\.............................................\verilog.rw
.....\........\.....\.............................................\_primary.dat
.....\........\.....\.............................................\_primary.dbs
.....\........\.....\.............................................\_primary.vhd
.....\........\.....\adder_subtracter_virtex4_7_0_ca4e72d019e5d592
.....\........\.....\.............................f0f86c7ab6cab538\verilog.asm
.....\........\.....\.............................................\verilog.rw
.....\........\.....\.............................................\_primary.dat
.....\........\.....\.............................................\_primary.dbs
.....\........\.....\.............................................\_primary.vhd
.....\........\.....\adder_subtracter_virtex4_7_0_f0f86c7ab6cab538
.....\........\.....\.lign_input\verilog.asm
.....\........\.....\...........\verilog.rw
.....\........\.....\...........\_primary.dat
.....\........\.....\...........\_primary.dbs
.....\........\.....\...........\_primary.vhd
.....\........\.....\align_input
.....\........\.....\binary_counter_virtex4_7_0_8c95a38a32cd3add\verilog.asm
.....\........\.....\...........................................\verilog.rw
.....\........\.....\...........................................\_primary.dat
.....\........\.....\...........................................\_primary.dbs
.....\........\.....\...........................................\_primary.vhd
.....\........\.....\binary_counter_virtex4_7_0_8c95a38a32cd3add
.....\........\.....\.mg_24_vx4_e54e5a776fc5110c\verilog.asm
.....\........\.....\...........................\verilog.rw
.....\........\.....\...........................\_primary.dat
.....\........\.....\...........................\_primary.dbs
.....\........\.....\...........................\_primary.vhd
.....\........\.....\bmg_24_vx4_e54e5a776fc5110c
.....\........\.....\cast\verilog.asm
.....\........\.....\....\verilog.rw
.....\........\.....\....\_primary.dat
.....\........\.....\....\_primary.dbs
.....\........\.....\....\_primary.vhd
.....\........\.....\cast
.....\........\.....\.lock_pkg\verilog.asm
.....\........\.....\.........\verilog.rw
.....\........\.....\.........\_primary.dat
.....\........\.....\.........\_primary.dbs
.....\........\.....\.........\_primary.vhd
.....\........\.....\clock_pkg
.....\........\.....\.oncat_4544c14410\verilo
.....\adder_subtracter_virtex4_7_0_159cd80bedeb8dd7.ngo
.....\adder_subtracter_virtex4_7_0_a05976c5f0c94e14.edn
.....\adder_subtracter_virtex4_7_0_a05976c5f0c94e14.ngo
.....\adder_subtracter_virtex4_7_0_ca4e72d019e5d592.edn
.....\adder_subtracter_virtex4_7_0_ca4e72d019e5d592.ngo
.....\adder_subtracter_virtex4_7_0_f0f86c7ab6cab538.edn
.....\adder_subtracter_virtex4_7_0_f0f86c7ab6cab538.ngo
.....\binary_counter_virtex4_7_0_8c95a38a32cd3add.edn
.....\binary_counter_virtex4_7_0_8c95a38a32cd3add.ngo
.....\bmg_24_vx4_e54e5a776fc5110c.mif
.....\bmg_24_vx4_e54e5a776fc5110c.ngc
.....\globals
.....\hdlFiles
.....\modelsim\sobel\adder_subtracter_virtex4_7_0_159cd80bedeb8dd7\verilog.asm
.....\........\.....\.............................................\verilog.rw
.....\........\.....\.............................................\_primary.dat
.....\........\.....\.............................................\_primary.dbs
.....\........\.....\.............................................\_primary.vhd
.....\........\.....\adder_subtracter_virtex4_7_0_159cd80bedeb8dd7
.....\........\.....\.............................a05976c5f0c94e14\verilog.asm
.....\........\.....\.............................................\verilog.rw
.....\........\.....\.............................................\_primary.dat
.....\........\.....\.............................................\_primary.dbs
.....\........\.....\.............................................\_primary.vhd
.....\........\.....\adder_subtracter_virtex4_7_0_a05976c5f0c94e14
.....\........\.....\.............................ca4e72d019e5d592\verilog.asm
.....\........\.....\.............................................\verilog.rw
.....\........\.....\.............................................\_primary.dat
.....\........\.....\.............................................\_primary.dbs
.....\........\.....\.............................................\_primary.vhd
.....\........\.....\adder_subtracter_virtex4_7_0_ca4e72d019e5d592
.....\........\.....\.............................f0f86c7ab6cab538\verilog.asm
.....\........\.....\.............................................\verilog.rw
.....\........\.....\.............................................\_primary.dat
.....\........\.....\.............................................\_primary.dbs
.....\........\.....\.............................................\_primary.vhd
.....\........\.....\adder_subtracter_virtex4_7_0_f0f86c7ab6cab538
.....\........\.....\.lign_input\verilog.asm
.....\........\.....\...........\verilog.rw
.....\........\.....\...........\_primary.dat
.....\........\.....\...........\_primary.dbs
.....\........\.....\...........\_primary.vhd
.....\........\.....\align_input
.....\........\.....\binary_counter_virtex4_7_0_8c95a38a32cd3add\verilog.asm
.....\........\.....\...........................................\verilog.rw
.....\........\.....\...........................................\_primary.dat
.....\........\.....\...........................................\_primary.dbs
.....\........\.....\...........................................\_primary.vhd
.....\........\.....\binary_counter_virtex4_7_0_8c95a38a32cd3add
.....\........\.....\.mg_24_vx4_e54e5a776fc5110c\verilog.asm
.....\........\.....\...........................\verilog.rw
.....\........\.....\...........................\_primary.dat
.....\........\.....\...........................\_primary.dbs
.....\........\.....\...........................\_primary.vhd
.....\........\.....\bmg_24_vx4_e54e5a776fc5110c
.....\........\.....\cast\verilog.asm
.....\........\.....\....\verilog.rw
.....\........\.....\....\_primary.dat
.....\........\.....\....\_primary.dbs
.....\........\.....\....\_primary.vhd
.....\........\.....\cast
.....\........\.....\.lock_pkg\verilog.asm
.....\........\.....\.........\verilog.rw
.....\........\.....\.........\_primary.dat
.....\........\.....\.........\_primary.dbs
.....\........\.....\.........\_primary.vhd
.....\........\.....\clock_pkg
.....\........\.....\.oncat_4544c14410\verilo