文件名称:verilog_calculator
介绍说明－－下载内容均来自于网络，请自行研究使用
一个Verilog写的简易计算器。能进行二进制加减乘除运算，操作数通过按键输入并用数码管显示。当按下运算符号键后，计算器进行两个数的运算，数码管将结果显示出来。-A simple calculator written in Verilog. Binary addition and subtraction to multiplication and division, operating a few keystrokes and use digital display. When the press operator symbol key, calculator computation of two numbers, the digital control will display the results.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
verilog\db\scan_test.asm.qmsg
.......\..\scan_test.cbx.xml
.......\..\scan_test.cmp.cdb
.......\..\scan_test.cmp.hdb
.......\..\scan_test.cmp.kpt
.......\..\scan_test.cmp.logdb
.......\..\scan_test.cmp.rdb
.......\..\scan_test.cmp.tdb
.......\..\scan_test.cmp0.ddb
.......\..\scan_test.dbp
.......\..\scan_test.db_info
.......\..\scan_test.eco.cdb
.......\..\scan_test.fit.qmsg
.......\..\scan_test.hier_info
.......\..\scan_test.hif
.......\..\scan_test.map.cdb
.......\..\scan_test.map.hdb
.......\..\scan_test.map.logdb
.......\..\scan_test.map.qmsg
.......\..\scan_test.pre_map.cdb
.......\..\scan_test.pre_map.hdb
.......\..\scan_test.psp
.......\..\scan_test.rtlv.hdb
.......\..\scan_test.rtlv_sg.cdb
.......\..\scan_test.rtlv_sg_swap.cdb
.......\..\scan_test.sgdiff.cdb
.......\..\scan_test.sgdiff.hdb
.......\..\scan_test.signalprobe.cdb
.......\..\scan_test.sld_design_entry.sci
.......\..\scan_test.sld_design_entry_dsc.sci
.......\..\scan_test.smp_dump.txt
.......\..\scan_test.syn_hier_info
.......\..\scan_test.tan.qmsg
.......\scan_test.asm.rpt
.......\scan_test.done
.......\scan_test.fit.rpt
.......\scan_test.fit.smsg
.......\scan_test.fit.summary
.......\scan_test.flow.rpt
.......\scan_test.map.rpt
.......\scan_test.map.summary
.......\scan_test.pin
.......\scan_test.pof
.......\scan_test.qpf
.......\scan_test.qsf
.......\scan_test.qws
.......\scan_test.sof
.......\scan_test.tan.rpt
.......\scan_test.tan.summary
.......\scan_test.v
.......\db
verilog
.......\..\scan_test.cbx.xml
.......\..\scan_test.cmp.cdb
.......\..\scan_test.cmp.hdb
.......\..\scan_test.cmp.kpt
.......\..\scan_test.cmp.logdb
.......\..\scan_test.cmp.rdb
.......\..\scan_test.cmp.tdb
.......\..\scan_test.cmp0.ddb
.......\..\scan_test.dbp
.......\..\scan_test.db_info
.......\..\scan_test.eco.cdb
.......\..\scan_test.fit.qmsg
.......\..\scan_test.hier_info
.......\..\scan_test.hif
.......\..\scan_test.map.cdb
.......\..\scan_test.map.hdb
.......\..\scan_test.map.logdb
.......\..\scan_test.map.qmsg
.......\..\scan_test.pre_map.cdb
.......\..\scan_test.pre_map.hdb
.......\..\scan_test.psp
.......\..\scan_test.rtlv.hdb
.......\..\scan_test.rtlv_sg.cdb
.......\..\scan_test.rtlv_sg_swap.cdb
.......\..\scan_test.sgdiff.cdb
.......\..\scan_test.sgdiff.hdb
.......\..\scan_test.signalprobe.cdb
.......\..\scan_test.sld_design_entry.sci
.......\..\scan_test.sld_design_entry_dsc.sci
.......\..\scan_test.smp_dump.txt
.......\..\scan_test.syn_hier_info
.......\..\scan_test.tan.qmsg
.......\scan_test.asm.rpt
.......\scan_test.done
.......\scan_test.fit.rpt
.......\scan_test.fit.smsg
.......\scan_test.fit.summary
.......\scan_test.flow.rpt
.......\scan_test.map.rpt
.......\scan_test.map.summary
.......\scan_test.pin
.......\scan_test.pof
.......\scan_test.qpf
.......\scan_test.qsf
.......\scan_test.qws
.......\scan_test.sof
.......\scan_test.tan.rpt
.......\scan_test.tan.summary
.......\scan_test.v
.......\db
verilog