文件名称:stratixIII_3sl150_dev_TSE_SGMII_v1

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [MacOS] [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 6.91mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 杨**
  • 相关连接:
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  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

该程序实现altera开发板 stratix III 3S150通过以太网与pc之间通信。 使用Quartus II和Nios II 设计。

因为altera官方没有这块板子的正确网卡与pc通信的程序,-Overall

This example works at 1000M/100M/10M Base SGMII mode on SIII 3S150 Kit.

Designed by Quartus II/IP Cores/Nios II EDS v8.0

This is not an official released Design Example. It is only for your reference, but beyond the support area of ALTERA Mysupport.

相关搜索: NIOS
II
EDS
stratix
3

(系统自动生成,下载前可以参看下载内容)

下载文件列表

stratixIII_3sl150_dev_TSE_SGMII_v1\.sopc_builder

..................................\.............\install.ptf

..................................\.............\install2.ptf

..................................\.............\preferences.xml

..................................\altmemddr.html

..................................\altmemddr.ppf

..................................\altmemddr.qip

..................................\altmemddr.v

..................................\altmemddr_advisor.ipa

..................................\altmemddr_auk_ddr_hp_controller_wrapper.v

..................................\altmemddr_bridge.v

..................................\altmemddr_controller_phy.v

..................................\altmemddr_example_driver.v

..................................\altmemddr_example_top.sdc

..................................\altmemddr_example_top.v

..................................\altmemddr_example_top.v.tmp

..................................\altmemddr_example_top.v.tmp2

..................................\altmemddr_example_top_2.v

..................................\altmemddr_example_top_3.v

..................................\altmemddr_example_top_4.v

..................................\altmemddr_example_top_5.v

..................................\altmemddr_example_top_6.v

..................................\altmemddr_example_top_7.v

..................................\altmemddr_ex_lfsr8.v

..................................\altmemddr_phy.html

..................................\altmemddr_phy.qip

..................................\altmemddr_phy.v

..................................\altmemddr_phy_alt_mem_phy_pll_siii.bsf

..................................\altmemddr_phy_alt_mem_phy_pll_siii.ppf

..................................\altmemddr_phy_alt_mem_phy_pll_siii.qip

..................................\altmemddr_phy_alt_mem_phy_pll_siii.v

..................................\altmemddr_phy_alt_mem_phy_pll_siii.v_.bak

..................................\altmemddr_phy_alt_mem_phy_pll_siii_bb.v

..................................\altmemddr_phy_alt_mem_phy_pll_siii_inst.v

..................................\altmemddr_phy_alt_mem_phy_sequencer_wrapper.v

..................................\altmemddr_phy_alt_mem_phy_siii.v

..................................\altmemddr_phy_assign_dq_groups.tcl

..................................\altmemddr_phy_autodetectedpins.tcl

..................................\altmemddr_phy_ddr_pins.tcl

..................................\altmemddr_phy_ddr_timing.sdc

..................................\altmemddr_phy_report_timing.tcl

..................................\altmemddr_phy_simgen_init.txt

..................................\altmemddr_phy_summary.csv

..................................\altmemddr_pin_assignments.tcl

..................................\altpllsys_pll.bsf

..................................\altpllsys_pll.ppf

..................................\altpllsys_pll.qip

..................................\altpllsys_pll.v

..................................\altpllsys_pll_bb.v

..................................\altpllsys_pll_inst.v

..................................\alt_mem_phy_defines.v

..................................\alt_mem_phy_sequencer.vhd

..................................\auk_ddr2_hp_init.ocp

..................................\auk_ddr_hp_controller.vhd

..................................\button_pio.v

..................................\clock_0.v

..................................\cpu.ocp

..................................\cpu.sdc

..................................\cpu.v

..................................\cpu_bht_ram.mif

..................................\cpu_dc_tag_ram.mif

..................................\cpu_ic_tag_ram.mif

..................................\cpu_interrupt_vector.v

..................................\cpu_jtag_debug_module.v

..................................\cpu_jtag_debug_module_sysclk.v

..................................\cpu_jtag_debug_module_tck.v

..................................\cpu_jtag_debug_module_wrapper.v

..................................\cpu_mult_cell.v

...............................

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