文件名称:memory

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [HTML]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 8.38mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • s*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

DESIGN A SINGLE PORT MEMORY 8*256 using array with standard logic & tri_state gate, and simulate it by reading & writing word
(系统自动生成,下载前可以参看下载内容)

下载文件列表

memory

......\db

......\..\logic_util_heursitic.dat

......\..\mux_dqc.tdf

......\..\prev_cmp_single_port_ram.asm.qmsg

......\..\prev_cmp_single_port_ram.eda.qmsg

......\..\prev_cmp_single_port_ram.fit.qmsg

......\..\prev_cmp_single_port_ram.map.qmsg

......\..\prev_cmp_single_port_ram.qmsg

......\..\prev_cmp_single_port_ram.sim.qmsg

......\..\prev_cmp_single_port_ram.tan.qmsg

......\..\single_port_ram.asm.qmsg

......\..\single_port_ram.asm.rdb

......\..\single_port_ram.asm_labs.ddb

......\..\single_port_ram.cbx.xml

......\..\single_port_ram.cmp.bpm

......\..\single_port_ram.cmp.cdb

......\..\single_port_ram.cmp.ecobp

......\..\single_port_ram.cmp.hdb

......\..\single_port_ram.cmp.kpt

......\..\single_port_ram.cmp.logdb

......\..\single_port_ram.cmp.rdb

......\..\single_port_ram.cmp.tdb

......\..\single_port_ram.cmp0.ddb

......\..\single_port_ram.cmp2.ddb

......\..\single_port_ram.cmp_merge.kpt

......\..\single_port_ram.db_info

......\..\single_port_ram.eco.cdb

......\..\single_port_ram.eda.qmsg

......\..\single_port_ram.eds_overflow

......\..\single_port_ram.fit.qmsg

......\..\single_port_ram.fnsim.cdb

......\..\single_port_ram.fnsim.hdb

......\..\single_port_ram.fnsim.qmsg

......\..\single_port_ram.hier_info

......\..\single_port_ram.hif

......\..\single_port_ram.lpc.html

......\..\single_port_ram.lpc.rdb

......\..\single_port_ram.lpc.txt

......\..\single_port_ram.map.bpm

......\..\single_port_ram.map.cdb

......\..\single_port_ram.map.ecobp

......\..\single_port_ram.map.hdb

......\..\single_port_ram.map.kpt

......\..\single_port_ram.map.logdb

......\..\single_port_ram.map.qmsg

......\..\single_port_ram.map_bb.cdb

......\..\single_port_ram.map_bb.hdb

......\..\single_port_ram.map_bb.logdb

......\..\single_port_ram.pre_map.cdb

......\..\single_port_ram.pre_map.hdb

......\..\single_port_ram.ram0_extra_memory_8996d293.hdl.mif

......\..\single_port_ram.rpp.qmsg

......\..\single_port_ram.rtlv.hdb

......\..\single_port_ram.rtlv_sg.cdb

......\..\single_port_ram.rtlv_sg_swap.cdb

......\..\single_port_ram.sgate.rvd

......\..\single_port_ram.sgate_sm.rvd

......\..\single_port_ram.sgdiff.cdb

......\..\single_port_ram.sgdiff.hdb

......\..\single_port_ram.sim.cvwf

......\..\single_port_ram.sim.hdb

......\..\single_port_ram.sim.qmsg

......\..\single_port_ram.sim.rdb

......\..\single_port_ram.simfam

......\..\single_port_ram.sld_design_entry.sci

......\..\single_port_ram.sld_design_entry_dsc.sci

......\..\single_port_ram.smart_action.txt

......\..\single_port_ram.syn_hier_info

......\..\single_port_ram.tan.qmsg

......\..\single_port_ram.tis_db_list.ddb

......\..\wed.wsf

......\extra_memory.vhd

......\extra_memory.vhd.bak

......\incremental_db

......\..............\compiled_partitions

......\..............\...................\single_port_ram.root_partition.cmp.cdb

......\..............\...................\single_port_ram.root_partition.cmp.dfp

......\..............\...................\single_port_ram.root_partition.cmp.hdb

......\..............\...................\single_port_ram.root_partition.cmp.kpt

......\..............\...................\single_port_ram.root_partition.cmp.logdb

......\..............\...................\single_port_ram.root_partition.cmp.rcfdb

......\..............\...................\single_port_ram.root_partition.cmp.re.rcfdb

......\..............\...................\single_port_ram.root_partition.map.cdb

......\..............\...................\single_port_ram.root_partition.map.dpi

......\..............\...................\single_port_ram.root_partition.map.hdb

......\..............\...................\single_port_ram.root_partition.map.kpt

......\..............\README

......\simulation

......\..........\modelsim

......\..........\........\single_port_ram.sft

......\..........\........\single_port_ram.vho

......\..........\........\single_port_ram_modelsim.xrf

......\..........\........\single_port_ram_vhd.sdo

......\single_port_ram.asm.rpt

......\single_port_ram.done

......\single_port_ram.eda.rpt

......\single_port_ram.fit.rpt

......\single_port_ram.fit.summary

......\single_port_ram.flow.rpt

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 本站是交换下载平台,提供交流渠道,下载内容来自于网络,除下载问题外,其它问题请自行百度更多...
  • 请直接用浏览器下载本站内容,不要使用迅雷之类的下载软件,用WinRAR最新版进行解压.
  • 如果您发现内容无法下载,请稍后再次尝试;或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎,请到消费记录里找到下载记录反馈给我们,经确认后退回积分.
  • 如下载前有疑问,可以通过点击"提供者"的名字,查看对方的联系方式,联系对方咨询.

相关评论

暂无评论内容.

发表评论

*主  题:
*内  容:
*验 证 码:

源码中国 www.ymcn.org