文件名称:ViterbiFPGA
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探讨了CDMA 数字移动通信中的差错控制问题, 研究用约束度K = 9 的卷积编码
和最大似然V iterbi 译码的差错控制方案. 在V iterbi 译码算法中, 提出了原位运算度量、保
存路径转移过程和循环存取幸存路径等方法, 能有效地减少存储量、降低功耗, 使得K =
9 的V iterbi 译码算法可在以单片XC4010 FPGA 为主的器件上实现, 其性能指标符合CD2
MA 数字移动通信IS 95 标准要求. 文中给出了实测的算法性能, 讨论了FPGA 具体实现
问题.-Discussion 了 CDMA digital mobile communication error control problems, research with the constraint degree K = 9 convolutional coding and maximum likelihood V iterbi error control coding scheme. In V iterbi decoding algorithm, the proposed in situ expression Duoliang save the transfer process and cycle path to access the surviving path and so on, can effectively reduce the storage capacity, lower power consumption, making the K = 9 of the V iterbi decoding algorithm can be based on the single XC4010 FPGA devices to achieve their performance indicators in line with CD2 MA IS 95 digital mobile communications standard. paper presents the measured performance of the algorithm, discuss the specific FPGA realization.
和最大似然V iterbi 译码的差错控制方案. 在V iterbi 译码算法中, 提出了原位运算度量、保
存路径转移过程和循环存取幸存路径等方法, 能有效地减少存储量、降低功耗, 使得K =
9 的V iterbi 译码算法可在以单片XC4010 FPGA 为主的器件上实现, 其性能指标符合CD2
MA 数字移动通信IS 95 标准要求. 文中给出了实测的算法性能, 讨论了FPGA 具体实现
问题.-Discussion 了 CDMA digital mobile communication error control problems, research with the constraint degree K = 9 convolutional coding and maximum likelihood V iterbi error control coding scheme. In V iterbi decoding algorithm, the proposed in situ expression Duoliang save the transfer process and cycle path to access the surviving path and so on, can effectively reduce the storage capacity, lower power consumption, making the K = 9 of the V iterbi decoding algorithm can be based on the single XC4010 FPGA devices to achieve their performance indicators in line with CD2 MA IS 95 digital mobile communications standard. paper presents the measured performance of the algorithm, discuss the specific FPGA realization.
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ViterbiFPGA.pdf