文件名称:counter
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-- Mod-16 Counter using JK Flip-flops
-- Structural descr iption of a 4-bit binary counter.
-- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively.
-- These are then packaged together along with a signal named tied_high into a package named jkpack .
-- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package.
-- The flip-flops and AND-gates are wired together to form a counter.
-- Notice the use of the keyword OPEN to indicate an open-cct output port.
-- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"--- Mod-16 Counter using JK Flip-flops
-- Structural descr iption of a 4-bit binary counter.
-- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively.
-- These are then packaged together along with a signal named tied_high into a package named jkpack .
-- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package.
-- The flip-flops and AND-gates are wired together to form a counter.
-- Notice the use of the keyword OPEN to indicate an open-cct output port.
-- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"
-- Structural descr iption of a 4-bit binary counter.
-- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively.
-- These are then packaged together along with a signal named tied_high into a package named jkpack .
-- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package.
-- The flip-flops and AND-gates are wired together to form a counter.
-- Notice the use of the keyword OPEN to indicate an open-cct output port.
-- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"--- Mod-16 Counter using JK Flip-flops
-- Structural descr iption of a 4-bit binary counter.
-- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively.
-- These are then packaged together along with a signal named tied_high into a package named jkpack .
-- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package.
-- The flip-flops and AND-gates are wired together to form a counter.
-- Notice the use of the keyword OPEN to indicate an open-cct output port.
-- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"
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counter.txt