文件名称:i2c

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [C/C++] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.06mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • Athe****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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I2c通信协议的Verilog实现,包括详细的设计说明和完整的文档-Verilog I2c communication protocol implementation, including detailed design specifications and complete documentation
相关搜索: i2c
i2c_master_byte_ctrl

(系统自动生成,下载前可以参看下载内容)

下载文件列表

i2c\tags\asyst_2\rtl\verilog\i2c_master_bit_ctrl.v

...\....\.......\...\.......\i2c_master_byte_ctrl.v

...\....\.......\...\.......\i2c_master_defines.v

...\....\.......\...\.......\i2c_master_top.v

...\....\.......\...\.......\timescale.v

...\....\......3\rtl\verilog\i2c_master_bit_ctrl.v

...\....\.......\...\.......\i2c_master_byte_ctrl.v

...\....\.......\...\.......\i2c_master_defines.v

...\....\.......\...\.......\i2c_master_top.v

...\....\.......\...\.......\timescale.v

...\....\first\I2C.VHD

...\....\.....\tst_ds1621.vhd

...\....\rel_1\bench\verilog\i2c_slave_model.v

...\....\.....\.....\.......\tst_bench_top.v

...\....\.....\.....\.......\wb_master_model.v

...\....\.....\doc\i2c_specs.pdf

...\....\.....\...\src\I2C_specs.doc

...\....\.....\rtl\verilog\i2c_master_bit_ctrl.v

...\....\.....\...\.......\i2c_master_byte_ctrl.v

...\....\.....\...\.......\i2c_master_defines.v

...\....\.....\...\.......\i2c_master_top.v

...\....\.....\...\.......\timescale.v

...\....\.....\...\.hdl\I2C.VHD

...\....\.....\...\....\i2c_master_bit_ctrl.vhd

...\....\.....\...\....\i2c_master_byte_ctrl.vhd

...\....\.....\...\....\i2c_master_top.vhd

...\....\.....\...\....\readme

...\....\.....\...\....\tst_ds1621.vhd

...\....\.....\sim\i2c_verilog\run\bench.vcd

...\....\.....\...\...........\...\ncverilog.key

...\....\.....\...\...........\...\ncverilog.log

...\....\.....\...\...........\...\run

...\....\.....\.oftware\include\oc_i2c_master.h

...\.runk\bench\verilog\i2c_slave_model.v

...\.....\.....\.......\spi_slave_model.v

...\.....\.....\.......\tst_bench_top.v

...\.....\.....\.......\wb_master_model.v

...\.....\doc\i2c_specs.pdf

...\.....\...\src\I2C_specs.doc

...\.....\rtl\verilog\i2c_master_bit_ctrl.v

...\.....\...\.......\i2c_master_byte_ctrl.v

...\.....\...\.......\i2c_master_defines.v

...\.....\...\.......\i2c_master_top.v

...\.....\...\.......\timescale.v

...\.....\...\.hdl\I2C.VHD

...\.....\...\....\i2c_master_bit_ctrl.vhd

...\.....\...\....\i2c_master_byte_ctrl.vhd

...\.....\...\....\i2c_master_top.vhd

...\.....\...\....\readme

...\.....\...\....\tst_ds1621.vhd

...\.....\sim\i2c_verilog\run\bench.vcd

...\.....\...\...........\...\ncverilog.key

...\.....\...\...........\...\ncverilog.log

...\.....\...\...........\...\run

...\.....\.oftware\include\oc_i2c_master.h

...\web_uploads\Block.gif

...\...........\i2c_rev03.pdf

...\...........\index.shtml

...\...........\index_orig.shtml

...\tags\rel_1\sim\i2c_verilog\run

...\....\asyst_2\rtl\verilog

...\....\......3\rtl\verilog

...\....\rel_1\bench\verilog

...\....\.....\doc\src

...\....\.....\rtl\verilog

...\....\.....\...\vhdl

...\....\.....\sim\i2c_verilog

...\....\.....\.oftware\include

...\.runk\sim\i2c_verilog\run

...\.ags\asyst_2\rtl

...\....\......3\rtl

...\....\rel_1\bench

...\....\.....\doc

...\....\.....\rtl

...\....\.....\sim

...\....\.....\software

...\.runk\bench\verilog

...\.....\doc\src

...\.....\rtl\verilog

...\.....\...\vhdl

...\.....\sim\i2c_verilog

...\.....\.oftware\include

...\.ags\asyst_2

...\....\asyst_3

...\....\first

...\....\rel_1

...\.runk\bench

...\.....\doc

...\.....\rtl

...\.....\sim

...\.....\software

...\tags

...\trunk

...\web_uploads

i2c

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