文件名称:Verilog-to-VHDL-translator
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描述了一个Verilog到VHDL翻译器的设计与实现。首先将Verilog模块转换为中间格式，然后按照预定义的翻译规则，生成功能等价的VHDL设计实体。该翻译器目前只支持Verilog的一个子集。通过Verilog-to-VHDL，
使得在Verilog．VHDL混合设计环境中重用Verilog设计成为可能。-Describes a Verilog to VHDL translator design and implementation. Verilog module into first intermediate format, then translated according to predefined rules to generate functional equivalent VHDL design entity. The translator currently supports only a subset of Verilog. By Verilog-to-VHDL, makes the Verilog. Mixed VHDL Verilog design environment design reuse possible.
使得在Verilog．VHDL混合设计环境中重用Verilog设计成为可能。-Describes a Verilog to VHDL translator design and implementation. Verilog module into first intermediate format, then translated according to predefined rules to generate functional equivalent VHDL design entity. The translator currently supports only a subset of Verilog. By Verilog-to-VHDL, makes the Verilog. Mixed VHDL Verilog design environment design reuse possible.
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Verilog-to-VHDL translator.pdf