文件名称:digital-clock-

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 158kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 西*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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本代码采用verilog HDL语言编写。实现的是数字跑表计时功能-The code using verilog HDL language. Implementation is a digital stopwatch timer functions
相关搜索: digital
clock
works
using
verilog
hdl

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下载文件列表

典型实例3_1 数字跑表\实战训练3 数字跑表\project\.untf

....................\..................\.......\bitgen.ut

....................\..................\.......\paobiao.bgn

....................\..................\.......\paobiao.bit

....................\..................\.......\paobiao.bld

....................\..................\.......\paobiao.cmd_log

....................\..................\.......\paobiao.dhp

....................\..................\.......\paobiao.drc

....................\..................\.......\paobiao.ise

....................\..................\.......\paobiao.ise_ISE_Backup

....................\..................\.......\paobiao.lso

....................\..................\.......\paobiao.mrp

....................\..................\.......\paobiao.nc1

....................\..................\.......\paobiao.ncd

....................\..................\.......\paobiao.ngc

....................\..................\.......\paobiao.ngd

....................\..................\.......\paobiao.ngm

....................\..................\.......\paobiao.ngr

....................\..................\.......\paobiao.pad

....................\..................\.......\paobiao.pad_txt

....................\..................\.......\paobiao.par

....................\..................\.......\paobiao.pcf

....................\..................\.......\paobiao.placed_ncd_tracker

....................\..................\.......\paobiao.prj

....................\..................\.......\paobiao.routed_ncd_tracker

....................\..................\.......\paobiao.stx

....................\..................\.......\paobiao.syr

....................\..................\.......\paobiao.twr

....................\..................\.......\paobiao.twx

....................\..................\.......\paobiao.ut

....................\..................\.......\paobiao.v

....................\..................\.......\paobiao.xpi

....................\..................\.......\paobiao_last_par.ncd

....................\..................\.......\paobiao_map.ncd

....................\..................\.......\paobiao_map.ngm

....................\..................\.......\paobiao_pad.csv

....................\..................\.......\paobiao_pad.txt

....................\..................\.......\paobiao_summary.html

....................\..................\.......\paobiao_tb.ant

....................\..................\.......\paobiao_tb.fdo

....................\..................\.......\paobiao_tb.jhd

....................\..................\.......\paobiao_tb.tbw

....................\..................\.......\paobiao_tb.tfw

....................\..................\.......\paobiao_tb.udo

....................\..................\.......\paobiao_tb.xwv

....................\..................\.......\paobiao_tb.xwv_bak

....................\..................\.......\paobiao_tb_bencher.prj

....................\..................\.......\paobiao_tb_tb.v

....................\..................\.......\paobiao_tb_tb.v.bak

....................\..................\.......\paobiao_vhdl.prj

....................\..................\.......\transcript

....................\..................\.......\vsim.wlf

....................\..................\.......\work\glbl\verilog.asm

....................\..................\.......\....\....\_primary.dat

....................\..................\.......\....\....\_primary.vhd

....................\..................\.......\....\paobiao\verilog.asm

....................\..................\.......\....\.......\_primary.dat

....................\..................\.......\....\.......\_primary.vhd

....................\..................\.......\....\......._tb\verilog.asm

....................\..................\.......\....\..........\_primary.dat

....................\..................\.......\....\..........\_primary.vhd

....................\..................\.......\....\_info

....................\..................\.......\xst\work\hdllib.ref

....................\..................\.......\...\....\vlg73

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