文件名称:spi_controller
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SPI控制器，基于VERILOG描述，分模块设计，共6个模块，时钟产生模块，移位模块，主模块，从模块，定义模块，顶层模块。-SPI controller, based on the VERILOG descr iption, sub-module design, a total of six modules, clock generation module, shift module, main module, from the modules, custom module, top module.
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下载文件列表
spi_controller\bench.vcd
..............\chart\Thumbs.db
..............\.....\图6-11.bmp
..............\.....\图6-12.bmp
..............\.....\图6-13.bmp
..............\.....\图6-14.bmp
..............\.....\图6-17.bmp
..............\.....\图6-18.bmp
..............\.....\图6-19.bmp
..............\.....\图6-7.bmp
..............\spi_clgen.v
..............\spi_controller.cr.mti
..............\spi_controller.mpf
..............\spi_defines.v
..............\spi_shift.v
..............\spi_slave_model.v
..............\spi_top.v
..............\tb_spi_top.v
..............\timescale.v
..............\transcript
..............\vsim.wlf
..............\wave\spi_clgen.bmp
..............\....\spi_shift.bmp
..............\....\spi_slave_model.bmp
..............\....\spi_top.bmp
..............\....\tb_spi_top.bmp
..............\....\Thumbs.db
..............\....\wb_master_model.bmp
..............\wb_master_model.v
..............\.ork\spi_clgen\verilog.asm
..............\....\.........\_primary.dat
..............\....\.........\_primary.vhd
..............\....\....shift\verilog.asm
..............\....\.........\_primary.dat
..............\....\.........\_primary.vhd
..............\....\.....lave_model\verilog.asm
..............\....\...............\_primary.dat
..............\....\...............\_primary.vhd
..............\....\....top\verilog.asm
..............\....\.......\_primary.dat
..............\....\.......\_primary.vhd
..............\....\tb_spi_top\verilog.asm
..............\....\..........\_primary.dat
..............\....\..........\_primary.vhd
..............\....\wb_master_model\verilog.asm
..............\....\...............\_primary.dat
..............\....\...............\_primary.vhd
..............\....\_info
..............\....\spi_clgen
..............\....\spi_shift
..............\....\spi_slave_model
..............\....\spi_top
..............\....\tb_spi_top
..............\....\wb_master_model
..............\chart
..............\wave
..............\work
spi_controller
..............\chart\Thumbs.db
..............\.....\图6-11.bmp
..............\.....\图6-12.bmp
..............\.....\图6-13.bmp
..............\.....\图6-14.bmp
..............\.....\图6-17.bmp
..............\.....\图6-18.bmp
..............\.....\图6-19.bmp
..............\.....\图6-7.bmp
..............\spi_clgen.v
..............\spi_controller.cr.mti
..............\spi_controller.mpf
..............\spi_defines.v
..............\spi_shift.v
..............\spi_slave_model.v
..............\spi_top.v
..............\tb_spi_top.v
..............\timescale.v
..............\transcript
..............\vsim.wlf
..............\wave\spi_clgen.bmp
..............\....\spi_shift.bmp
..............\....\spi_slave_model.bmp
..............\....\spi_top.bmp
..............\....\tb_spi_top.bmp
..............\....\Thumbs.db
..............\....\wb_master_model.bmp
..............\wb_master_model.v
..............\.ork\spi_clgen\verilog.asm
..............\....\.........\_primary.dat
..............\....\.........\_primary.vhd
..............\....\....shift\verilog.asm
..............\....\.........\_primary.dat
..............\....\.........\_primary.vhd
..............\....\.....lave_model\verilog.asm
..............\....\...............\_primary.dat
..............\....\...............\_primary.vhd
..............\....\....top\verilog.asm
..............\....\.......\_primary.dat
..............\....\.......\_primary.vhd
..............\....\tb_spi_top\verilog.asm
..............\....\..........\_primary.dat
..............\....\..........\_primary.vhd
..............\....\wb_master_model\verilog.asm
..............\....\...............\_primary.dat
..............\....\...............\_primary.vhd
..............\....\_info
..............\....\spi_clgen
..............\....\spi_shift
..............\....\spi_slave_model
..............\....\spi_top
..............\....\tb_spi_top
..............\....\wb_master_model
..............\chart
..............\wave
..............\work
spi_controller