文件名称:Syn_FIFO

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [PDF]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 2.69mb
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  • 0次
  • 提 供 者:
  • d**
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在libero环境下,FPGA如何使用ProASIC3/E的同步FIFO-In libero environment, FPGA using ProASIC3/E of the synchronous FIFO
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Syn_FIFO\SYN_FIFO\designer\impl1\designer.log

........\........\........\.....\FIFO_top.adb

........\........\........\.....\.........dtf\verify.log

........\........\........\.....\FIFO_top.ide_des

........\........\........\.....\FIFO_top.pdb

........\........\........\.....\FIFO_top.pdb.depends

........\........\........\.....\FIFO_top.tcl

........\........\........\.....\........_fp\FIFO_top.log

........\........\........\.....\...........\FIFO_top.pro

........\........\........\.....\...........\projectData\FIFO_top.pdb

........\........\hdl\ctrl_FIFO.v

........\........\...\FIFO_top.v

........\........\...\rec.v

........\........\...\send.v

........\........\simulation\meminit.dat

........\........\..........\modelsim.ini

........\........\..........\modelsim.ini.sav

........\........\.martgen\smartgen.aws

........\........\........\.yn_fifo\syn_fifo.cxf

........\........\........\........\syn_fifo.gen

........\........\........\........\syn_fifo.log

........\........\........\........\syn_fifo.v

........\........\........\syn_fifo_work.ixf

........\........\.ynthesis\.recordref

........\........\.........\FIFO_top.areasrr

........\........\.........\FIFO_top.edn

........\........\.........\FIFO_top.fse

........\........\.........\FIFO_top.htm

........\........\.........\FIFO_top.map

........\........\.........\FIFO_top.sap

........\........\.........\FIFO_top.sdf

........\........\.........\FIFO_top.srd

........\........\.........\FIFO_top.srm

........\........\.........\FIFO_top.srr

........\........\.........\FIFO_top.srs

........\........\.........\FIFO_top.tlg

........\........\.........\FIFO_top_sdc.sdc

........\........\.........\FIFO_top_syn.prj

........\........\.........\stdout.log

........\........\.........\.yntmp\FIFO_top.msg

........\........\.........\......\FIFO_top.plg

........\........\.........\......\FIFO_top_flink.htm

........\........\.........\......\FIFO_top_srr.htm

........\........\.........\......\FIFO_top_toc.htm

........\........\.........\......\sap.log

........\........\.........\traplog.tlg

........\........\SYN_FIFO.prj

........\........\viewdraw\vf\project.lst

........\........\........\viewdraw.ini

........\Syn_FIFO_lab.rar

........\同步FIFO实验例程.pdf

........\SYN_FIFO\designer\impl1\FIFO_top_fp\projectData

........\........\........\.....\FIFO_top.dtf

........\........\........\.....\FIFO_top_fp

........\........\........\.....\simulation

........\........\........\impl1

........\........\smartgen\syn_fifo

........\........\.ynthesis\syntmp

........\........\viewdraw\vf

........\........\designer

........\........\hdl

........\........\simulation

........\........\smartgen

........\........\synthesis

........\........\viewdraw

........\SYN_FIFO

Syn_FIFO

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