文件名称:buffer
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一个串行接收，并行发送的缓存器，其数据存储使用双端口SRAM（一读一写）实现，SRAM大小为深64、宽32位（64字×32位，使用提供的双端口SRAM见目录rf2shd4）。缓存器按一位串行输入接收数据，缓存器位置全满后不再接收串行数据输入；并根据读数请求，按接收数据的顺序，将接收完整的32位数据发送出去，并标记该缓存器位置为空，又可以放置新的串行输入数据。
设计了同步和异步两种串行发送方法。-Receive a serial, parallel send buffer, the data is stored using the dual-port SRAM (read write) to achieve the SRAM size
Deep 64 and 32 wide (64-word × 32-bit, see of directory rf2shd4), using the supplied dual-port SRAM. Buffer is connected by a serial input
Receiving data, the location of the buffers are full and no longer receive the serial data input and according to the reading request, the order to receive data, will take over
Received the full 32-bit data sent, and mark the location of the buffer is empty, can be placed on the new serial input data.
Both synchronous and asynchronous serial send method.
设计了同步和异步两种串行发送方法。-Receive a serial, parallel send buffer, the data is stored using the dual-port SRAM (read write) to achieve the SRAM size
Deep 64 and 32 wide (64-word × 32-bit, see of directory rf2shd4), using the supplied dual-port SRAM. Buffer is connected by a serial input
Receiving data, the location of the buffers are full and no longer receive the serial data input and according to the reading request, the order to receive data, will take over
Received the full 32-bit data sent, and mark the location of the buffer is empty, can be placed on the new serial input data.
Both synchronous and asynchronous serial send method.
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下载文件列表
实验提交\串行接收并行发送FIFO的设计与验证.docx
........\设计源码\SRAM\Memory.v
........\........\....\SRAM.v
........\........\....\Synchronous_Receive.v
........\........\....\test_Memory.v
........\........\....\test_SRAM.v
........\........\....\test_Synchronous_Receive.v
........\........\....2\Asynchronous_Receive.v
........\........\.....\Memory.v
........\........\.....\SRAM2.v
........\........\.....\test_Asynchronous_Receive.v
........\........\.....\test_Memory.v
........\........\.....\test_SRAM2.v
........\........\SRAM
........\........\SRAM2
........\设计源码
实验提交
........\设计源码\SRAM\Memory.v
........\........\....\SRAM.v
........\........\....\Synchronous_Receive.v
........\........\....\test_Memory.v
........\........\....\test_SRAM.v
........\........\....\test_Synchronous_Receive.v
........\........\....2\Asynchronous_Receive.v
........\........\.....\Memory.v
........\........\.....\SRAM2.v
........\........\.....\test_Asynchronous_Receive.v
........\........\.....\test_Memory.v
........\........\.....\test_SRAM2.v
........\........\SRAM
........\........\SRAM2
........\设计源码
实验提交