文件名称:DDS-design-based-on-verilog

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  • VHDL编程
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  • [PDF]
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  • 2012-11-26
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  • 1mb
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  • zhx****
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用verilog语言设计DDS数字频率合成器-DDS design based on verilog
(系统自动生成,下载前可以参看下载内容)

下载文件列表

基于Xilinx XUPV2P 的MP3播放器设计\DDS相关文档\DDS信号源的FPGA实现.doc

.................................\...........\FPGA实现DDS的设计.doc

.................................\...........\基于FPGA 的DDS 调频信号的研究与实现.pdf

.................................\...........\基于FPGA的直接数字频率合成技术设计.doc

.................................\ise\brute_force_synchronizer.v

.................................\...\button_press_unit.v

.................................\...\counter_k.v

.................................\...\dds.v

.................................\...\dds_dcm.v

.................................\...\dds_exam.ise

.................................\...\dds_exam.ise_ISE_Backup

.................................\...\dds_exam.ntrc_log

.................................\...\dds_exam.restore

.................................\...\dds_top.bld

.................................\...\dds_top.cmd_log

.................................\...\dds_top.lso

.................................\...\dds_top.ncd

.................................\...\dds_top.ngc

.................................\...\dds_top.ngd

.................................\...\dds_top.ngr

.................................\...\dds_top.pad

.................................\...\dds_top.par

.................................\...\dds_top.pcf

.................................\...\dds_top.prj

.................................\...\dds_top.stx

.................................\...\dds_top.syr

.................................\...\dds_top.twr

.................................\...\dds_top.twx

.................................\...\dds_top.ucf

.................................\...\dds_top.unroutes

.................................\...\dds_top.v

.................................\...\dds_top.v.bak

.................................\...\dds_top.xpi

.................................\...\dds_top.xst

.................................\...\dds_top_guide.ncd

.................................\...\dds_top_map.map

.................................\...\dds_top_map.mrp

.................................\...\dds_top_map.ncd

.................................\...\dds_top_map.ngm

.................................\...\dds_top_pad.csv

.................................\...\dds_top_pad.txt

.................................\...\dds_top_prev_built.ngd

.................................\...\dds_top_summary.html

.................................\...\dds_top_summary.xml

.................................\...\dds_top_usage.xml

.................................\...\debouncer.v

.................................\...\div_N.v

.................................\...\ff_lib.v

.................................\...\one_pulse.v

.................................\...\sine_rom.v

.................................\...\transcript

.................................\...\xst\dump.xst\dds_top.prj\ntrc.scr

.................................\...\...\work\hdllib.ref

.................................\...\...\....\vlg03\debouncer.bin

.................................\...\...\....\....7\dffre.bin

.................................\...\...\....\...10\add12.bin

.................................\...\...\....\....4\add16.bin

.................................\...\...\....\....7\add24.bin

.................................\...\...\....\....8\div___n.bin

.................................\...\...\....\....9\conadder__4bits.bin

.................................\...\...\....\...28\dff.bin

.................................\...\...\....\....B\dds.bin

.................................\...\...\....\...33\button__press__unit.bin

.................................\...\...\....\....9\brute__force__synchronizer.bin

.................................\...\...\....\....A\dffr.bin

.................................\...\...\....\...4D\dds__top.bin

.................................\...\...\....\...56\counter__k.bin

.................................\...\...\....\....E\one__pulse.bin

.................................\...\...\....\...60\sine__rom.bin

.................................\...\...\....\....5\adder__4bits.bin

.................................\...\...\....\...7E\dds__dcm.b

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