文件名称:USB-2.0-source-code-by-VHDL
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实现USB2.0接口控制的VHDL源代码\usb_funct\bench\CVS\Entries
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..............................\.........\.....\verilog\CVS\Entries
..............................\.........\.....\.......\...\Repository
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..............................\.........\doc\CVS\Entries
..............................\.........\...\...\Repository
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..............................\.........\...\README.txt
..............................\.........\...\STATUS.txt
..............................\.........\...\usb_doc.pdf
..............................\.........\rtl\CVS\Entries
..............................\.........\...\...\Repository
..............................\.........\...\...\Root
..............................\.........\...\verilog\CVS\Entries
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..............................\.........\...\.......\usbf_crc16.v
..............................\.........\...\.......\usbf_crc5.v
..............................\.........\...\.......\usbf_defines.v
..............................\.........\...\.......\usbf_ep_rf.v
..............................\.........\...\.......\usbf_ep_rf_dummy.v
..............................\.........\...\.......\usbf_idma.v
..............................\.........\...\.......\usbf_mem_arb.v
..............................\.........\...\.......\usbf_pa.v
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..............................\.........\...\.......\usbf_pe.v
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..............................\.........\...\.......\usbf_rf.v
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..............................\.........\...\.......\usbf_utmi_if.v
..............................\.........\...\.......\usbf_utmi_ls.v
..............................\.........\...\.......\usbf_wb.v
..............................\.........\sim\CVS\Entries
..............................\.........\...\...\Repository
..............................\.........\...\...\Root
..............................\.........\...\rtl_sim\bin\CVS\Entries
..............................\.........\...\.......\...\...\Repository
..............................\.........\...\.......\...\...\Root
..............................\.........\...\.......\CVS\Entries
..............................\.........\...\.......\...\Repository
..............................\.........\...\.......\...\Root
..............................\.........\...\.......\run\CVS\Entries
..............................\.........\...\.......\...\...\Repository
..............................\.........\...\.......\...\...\Root
..............................\.........\.yn\bin\comp.dc
..............................\.........\...\...\CVS\Entries
..............................\.........\...\...\...\Repository
..............................\.........\...\...\...\Root
..............................\.........\...\...\design_spec.dc
..............................\.........\...\...\lib_spec.dc
..............................\.........\...\...\read.dc
..............................\.........\...\CVS\Entries
..............................\.........\...\...\Repository
..............................\.........\...\...\Root
..............................\.........\...\log\CVS\Entries
..............................\.........\...\...\...\Repository
..............................\.........\...\...\...\Root
..............................\.........\...\out\CVS\Entries
..............................\.........\...\...\...\Repository
..............................\.........\...\...\...\Root
..............................\.........\...\run\CVS\Entries
..............................\.........\...\...\...\Repository
..............................\.........\...\...\...\Root
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..............................\.........\.....\...\Repository
..............................\.........\.....\...\Root
..............................\.........\.....\verilog\CVS\Entries
..............................\.........\.....\.......\...\Repository
..............................\.........\.....\.......\...\Root
..............................\.........\doc\CVS\Entries
..............................\.........\...\...\Repository
..............................\.........\...\...\Root
..............................\.........\...\README.txt
..............................\.........\...\STATUS.txt
..............................\.........\...\usb_doc.pdf
..............................\.........\rtl\CVS\Entries
..............................\.........\...\...\Repository
..............................\.........\...\...\Root
..............................\.........\...\verilog\CVS\Entries
..............................\.........\...\.......\...\Repository
..............................\.........\...\.......\...\Root
..............................\.........\...\.......\usbf_crc16.v
..............................\.........\...\.......\usbf_crc5.v
..............................\.........\...\.......\usbf_defines.v
..............................\.........\...\.......\usbf_ep_rf.v
..............................\.........\...\.......\usbf_ep_rf_dummy.v
..............................\.........\...\.......\usbf_idma.v
..............................\.........\...\.......\usbf_mem_arb.v
..............................\.........\...\.......\usbf_pa.v
..............................\.........\...\.......\usbf_pd.v
..............................\.........\...\.......\usbf_pe.v
..............................\.........\...\.......\usbf_pl.v
..............................\.........\...\.......\usbf_rf.v
..............................\.........\...\.......\usbf_top.v
..............................\.........\...\.......\usbf_utmi_if.v
..............................\.........\...\.......\usbf_utmi_ls.v
..............................\.........\...\.......\usbf_wb.v
..............................\.........\sim\CVS\Entries
..............................\.........\...\...\Repository
..............................\.........\...\...\Root
..............................\.........\...\rtl_sim\bin\CVS\Entries
..............................\.........\...\.......\...\...\Repository
..............................\.........\...\.......\...\...\Root
..............................\.........\...\.......\CVS\Entries
..............................\.........\...\.......\...\Repository
..............................\.........\...\.......\...\Root
..............................\.........\...\.......\run\CVS\Entries
..............................\.........\...\.......\...\...\Repository
..............................\.........\...\.......\...\...\Root
..............................\.........\.yn\bin\comp.dc
..............................\.........\...\...\CVS\Entries
..............................\.........\...\...\...\Repository
..............................\.........\...\...\...\Root
..............................\.........\...\...\design_spec.dc
..............................\.........\...\...\lib_spec.dc
..............................\.........\...\...\read.dc
..............................\.........\...\CVS\Entries
..............................\.........\...\...\Repository
..............................\.........\...\...\Root
..............................\.........\...\log\CVS\Entries
..............................\.........\...\...\...\Repository
..............................\.........\...\...\...\Root
..............................\.........\...\out\CVS\Entries
..............................\.........\...\...\...\Repository
..............................\.........\...\...\...\Root
..............................\.........\...\run\CVS\Entries
..............................\.........\...\...\...\Repository
..............................\.........\...\...\...\Root
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