文件名称:ml605_PCIe_Gen1_x8_rdf0008_13.1_c

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 3.83mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • xia***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

ML605_Reference_Designs:ml605_PCIe_Gen2_x4_rdf0009,xilinx开发板的PCIe设计例程,包括源码和下载文件.verilog-ML605_Reference_Designs:PCIe codes and download files include ace and bit file
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ml605_pcie_x8_gen1\ml605_pcie_x8_gen1.cgc

..................\ml605_pcie_x8_gen1.cgp

..................\readme.txt

..................\....y_for_download\make_plat_mcs.bat

..................\..................\ml605_pcie_x8_gen1.cfi

..................\..................\ml605_pcie_x8_gen1.mcs

..................\..................\ml605_pcie_x8_gen1.prm

..................\..................\ml605_program_platflash.cmd

..................\v6_pcie_v1_7.gise

..................\v6_pcie_v1_7.veo

..................\v6_pcie_v1_7.xco

..................\v6_pcie_v1_7.xise

..................\............\example_design\EP_MEM.v

..................\............\..............\PIO.v

..................\............\..............\PIO_64.v

..................\............\..............\PIO_64_RX_ENGINE.v

..................\............\..............\PIO_64_TX_ENGINE.v

..................\............\..............\PIO_EP.v

..................\............\..............\PIO_EP_MEM_ACCESS.v

..................\............\..............\PIO_TO_CTRL.v

..................\............\..............\pci_exp_8_lane_64b_ep.v

..................\............\..............\pcie_app_v6.v

..................\............\..............\xilinx_pcie_2_0_ep_v6.v

..................\............\..............\xilinx_pcie_2_0_ep_v6_08_lane_gen1_xc6vlx240t-ff1156-1_ML605.ucf

..................\............\implement\implement.bat

..................\............\.........\implement.log

..................\............\.........\implement.sh

..................\............\.........\results\mapped.mrp

..................\............\.........\.......\routed.bit

..................\............\.........\.......\routed.ncd

..................\............\.........\.......\routed.pad

..................\............\.........\.......\routed.par

..................\............\.........\xilinx_pcie_2_0_ep_v6.cmd

..................\............\.........\xilinx_pcie_2_0_ep_v6.log

..................\............\.........\xilinx_pcie_2_0_ep_v6.ngc

..................\............\.........\xilinx_pcie_2_0_ep_v6.ngc_xst.xrpt

..................\............\.........\xilinx_pcie_2_0_ep_v6.ngr

..................\............\.........\xilinx_pcie_2_0_ep_v6.prj

..................\............\.........\xilinx_pcie_2_0_ep_v6.xcf

..................\............\.........\xst.srp

..................\............\source\gtx_drp_chanalign_fix_3752_v6.v

..................\............\......\gtx_rx_valid_filter_v6.v

..................\............\......\gtx_tx_sync_rate_v6.v

..................\............\......\gtx_wrapper_v6.v

..................\............\......\pcie_2_0_v6.v

..................\............\......\pcie_bram_top_v6.v

..................\............\......\pcie_bram_v6.v

..................\............\......\pcie_brams_v6.v

..................\............\......\pcie_clocking_v6.v

..................\............\......\pcie_gtx_v6.v

..................\............\......\pcie_pipe_lane_v6.v

..................\............\......\pcie_pipe_misc_v6.v

..................\............\......\pcie_pipe_v6.v

..................\............\......\pcie_reset_delay_v6.v

..................\............\......\pcie_upconfig_fix_3451_v6.v

..................\............\......\v6_pcie_v1_7.v

..................\............\v6_pcie_readme.txt

..................\v6_pcie_v1_7_flist.txt

..................\v6_pcie_v1_7_xmdf.tcl

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