文件名称:digital_clock

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 803kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • shis****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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verilog digital clock.四位 有计时器 有秒表 。是学生作业。 原创。 适合初步学习verilog的学生。 -verilog digital clock/4 bits/ up_down/stopwatch
(系统自动生成,下载前可以参看下载内容)

下载文件列表

digital_clock

.............\db

.............\..\digital_clock.asm.qmsg

.............\..\digital_clock.asm_labs.ddb

.............\..\digital_clock.cbx.xml

.............\..\digital_clock.cmp.bpm

.............\..\digital_clock.cmp.cdb

.............\..\digital_clock.cmp.ecobp

.............\..\digital_clock.cmp.hdb

.............\..\digital_clock.cmp.logdb

.............\..\digital_clock.cmp.rdb

.............\..\digital_clock.cmp.tdb

.............\..\digital_clock.cmp0.ddb

.............\..\digital_clock.cmp2.ddb

.............\..\digital_clock.cmp_bb.cdb

.............\..\digital_clock.cmp_bb.hdb

.............\..\digital_clock.cmp_bb.logdb

.............\..\digital_clock.cmp_bb.rcf

.............\..\digital_clock.dbp

.............\..\digital_clock.db_info

.............\..\digital_clock.eco.cdb

.............\..\digital_clock.eds_overflow

.............\..\digital_clock.fit.qmsg

.............\..\digital_clock.hier_info

.............\..\digital_clock.hif

.............\..\digital_clock.map.bpm

.............\..\digital_clock.map.cdb

.............\..\digital_clock.map.ecobp

.............\..\digital_clock.map.hdb

.............\..\digital_clock.map.logdb

.............\..\digital_clock.map.qmsg

.............\..\digital_clock.map_bb.cdb

.............\..\digital_clock.map_bb.hdb

.............\..\digital_clock.map_bb.logdb

.............\..\digital_clock.pre_map.cdb

.............\..\digital_clock.pre_map.hdb

.............\..\digital_clock.psp

.............\..\digital_clock.pss

.............\..\digital_clock.rtlv.hdb

.............\..\digital_clock.rtlv_sg.cdb

.............\..\digital_clock.rtlv_sg_swap.cdb

.............\..\digital_clock.sgdiff.cdb

.............\..\digital_clock.sgdiff.hdb

.............\..\digital_clock.signalprobe.cdb

.............\..\digital_clock.sim.cvwf

.............\..\digital_clock.sim.hdb

.............\..\digital_clock.sim.qmsg

.............\..\digital_clock.sim.rdb

.............\..\digital_clock.sld_design_entry.sci

.............\..\digital_clock.sld_design_entry_dsc.sci

.............\..\digital_clock.syn_hier_info

.............\..\digital_clock.tan.qmsg

.............\..\digital_clock.tis_db_list.ddb

.............\..\prev_cmp_digital_clock.asm.qmsg

.............\..\prev_cmp_digital_clock.fit.qmsg

.............\..\prev_cmp_digital_clock.map.qmsg

.............\..\prev_cmp_digital_clock.qmsg

.............\..\prev_cmp_digital_clock.sim.qmsg

.............\..\prev_cmp_digital_clock.tan.qmsg

.............\..\wed.wsf

.............\digital_clock.asm.rpt

.............\digital_clock.bdf

.............\digital_clock.cdf

.............\digital_clock.done

.............\digital_clock.dpf

.............\digital_clock.fit.rpt

.............\digital_clock.fit.smsg

.............\digital_clock.fit.summary

.............\digital_clock.flow.rpt

.............\digital_clock.map.rpt

.............\digital_clock.map.smsg

.............\digital_clock.map.summary

.............\digital_clock.pin

.............\digital_clock.pof

.............\digital_clock.qpf

.............\digital_clock.qsf

.............\digital_clock.qws

.............\digital_clock.sim.rpt

.............\digital_clock.sof

.............\digital_clock.tan.rpt

.............\digital_clock.tan.summary

.............\digital_clock.vwf

.............\digital_clock_assignment_defaults.qdf

.............\display.v

.............\display_combine2.bdf

.............\div_frequency.v

.............\frequency_divider.v

.............\frequency_divider.v.bak

.............\led1.v

.............\led1.v.bak

.............\led2.v

.............\led2.v.bak

.............\led3.v

.............\led3.v.bak

.............\led4.v

.............\led4.v.bak

.............\main_control.v

.............\main_control.v.bak

.............\main_control2.bdf

.............\prev_cmp_digital_clock.qmsg

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