文件名称:VerilogHDL-fpga

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 181kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 肖**
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精通VerilogHDL:IC设计核心技术实例详解-Proficient VerilogHDL: IC design example explanation of core technology
(系统自动生成,下载前可以参看下载内容)

下载文件列表

部分习题源码\ex2_2\demux.fsdb

............\.....\ex2_2.v

............\.....\rtl_wrk\ex2_2\verilog.asm

............\.....\.......\.....\_primary.dat

............\.....\.......\.....\_primary.vhd

............\.....\.......\_info

............\.....\run.do

............\....3\ex2_3.fsdb

............\.....\ex2_3.v

............\.....\ex2_3.v.bak

............\.....\rtl_wrk\ex2_3\verilog.asm

............\.....\.......\.....\_primary.dat

............\.....\.......\.....\_primary.vhd

............\.....\.......\_info

............\.....\run.do

............\....6\ex2_6.fsdb

............\.....\ex2_6.v

............\.....\rtl_wrk\ex2_6\verilog.asm

............\.....\.......\.....\_primary.dat

............\.....\.......\.....\_primary.vhd

............\.....\.......\_info

............\.....\run.do

............\..3_3\dff.prd

............\.....\dff.prj

............\.....\dff.v

............\.....\rev_1\dff.srr

............\..6_1\comp.v

............\.....\comp4.v

............\.....\ex6_1.v

............\.....\rtl_wrk\comp\verilog.asm

............\.....\.......\....\_primary.dat

............\.....\.......\....\_primary.vhd

............\.....\.......\....4\verilog.asm

............\.....\.......\.....\_primary.dat

............\.....\.......\.....\_primary.vhd

............\.....\.......\ex6_1\verilog.asm

............\.....\.......\.....\_primary.dat

............\.....\.......\.....\_primary.vhd

............\.....\.......\_info

............\.....\run.do

............\....3\mul.cr.mti

............\.....\mul.mpf

............\.....\mul.vcd

............\.....\rtl\mul.v

............\.....\..._wrk\ex4_13\verilog.asm

............\.....\.......\......\_primary.dat

............\.....\.......\......\_primary.vhd

............\.....\.......\mul\verilog.asm

............\.....\.......\...\_primary.dat

............\.....\.......\...\_primary.vhd

............\.....\.......\sfifo\verilog.asm

............\.....\.......\.....\_primary.dat

............\.....\.......\.....\_primary.vhd

............\.....\.......\.tackc\verilog.asm

............\.....\.......\......\_primary.dat

............\.....\.......\......\_primary.vhd

............\.....\.......\top\verilog.asm

............\.....\.......\...\_primary.dat

............\.....\.......\...\_primary.vhd

............\.....\.......\_info

............\.....\run.do

............\.....\top.v

............\.....\transcript

............\....4\cas.cr.mti

............\.....\cas.mpf

............\.....\csa.rc

............\.....\csa8_4.v

............\.....\rtl_wrk\csa8_4\verilog.asm

............\.....\.......\......\_primary.dat

............\.....\.......\......\_primary.vhd

............\.....\.......\top\verilog.asm

............\.....\.......\...\_primary.dat

............\.....\.......\...\_primary.vhd

............\.....\.......\_info

............\.....\run.do

............\.....\top.v

............\....5\ex6_5.cr.mti

............\.....\ex6_5.mpf

............\.....\ex6_5.v

............\.....\rtl_wrk\ex6_5\verilog.asm

............\.....\.......\.....\_primary.dat

............\.....\.......\.....\_primary.vhd

............\.....\.......\_info

............\.....\run.do

............\.....\work\_info

............\memory\debussy\run.f

............\......\mem.cr.mti

............\......\mem.mpf

............\......\RAM 96x96x 16bit.doc

............\......\rtl_wrk\mem96x96x16\verilog.asm

............\......\.......\...........\_primary.dat

............\......\.......\...........\_primary.vhd

............\......\.......\top\verilog.asm

............\......\.......\...\_primary.dat

............\......\.......\...\_primary.vhd

............\......\.......\_info

............\......\run.do

............\......\src\mem96x96x16.v

............\......\top.v

............\......\vsim_stacktrace.vstf

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