文件名称:FPGA-verilog-matlab

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [Matlab] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 204kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 虎***
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  • 下载说明:
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《无线通信FPGA设计》一书中例子的Matlab及verilog代码,非常详细-"Wireless FPGA design," a book example of Matlab and verilog code, very detailed
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无线通信FPGA设计

................\matlab代码

................\..........\matlab

................\..........\......\c10

................\..........\......\...\c.mat

................\..........\......\...\costas.m

................\..........\......\...\frame_syn.m

................\..........\......\...\PLLC.m

................\..........\......\...\RRCrece.m

................\..........\......\...\RRCsend.m

................\..........\......\...\symbol_syn.m

................\..........\......\c11

................\..........\......\...\adpeq.m

................\..........\......\...\ante.m

................\..........\......\...\FFTlms.m

................\..........\......\...\lms.m

................\..........\......\...\RLS.m

................\..........\......\...\signlms.m

................\..........\......\...\untitled.mat

................\..........\......\...\WHT.m

................\..........\......\...\WHTlms.m

................\..........\......\c12

................\..........\......\...\correce.m

................\..........\......\...\matchfil.m

................\..........\......\...\rake.m

................\..........\......\c13

................\..........\......\...\cell_search_cpich.m

................\..........\......\...\ovsf.m

................\..........\......\...\scramble.m

................\..........\......\...\wcdmasource.m

................\..........\......\c6

................\..........\......\..\impinvar_bilinear.m

................\..........\......\..\rcosflt_filter.m

................\..........\......\..\rcosine_filter.m

................\..........\......\c7

................\..........\......\..\cicde.m

................\..........\......\..\CICdec.m

................\..........\......\..\cicin.m

................\..........\......\..\CICinterp.m

................\..........\......\..\halfdec.m

................\..........\......\..\halfinterp.m

................\..........\......\..\hbfil.m

................\..........\......\..\multirece.m

................\..........\......\..\multisend.m

................\..........\......\c8

................\..........\......\..\ASKmod.m

................\..........\......\..\F2T.m

................\..........\......\..\LPF.m

................\..........\......\..\MSKmod.m

................\..........\......\..\OFDMmod.m

................\..........\......\..\QAMmod.m

................\..........\......\..\QPSKmod.m

................\..........\......\..\T2F.m

................\..........\......\c9

................\..........\......\..\convcode.m

................\..........\......\..\CRCcheck.m

................\..........\......\..\encoderm.m

................\..........\......\..\encode_bit.m

................\..........\......\..\hamming7_4.m

................\..........\......\..\intrlvcode.m

................\..........\......\..\RScode.m

................\..........\......\..\rsc_encode.m

................\..........\......\..\TCMcode.m

................\pudn.txt

................\Verilog代码

................\...........\c10

................\...........\...\10-2

................\...........\...\....\mult.xco

................\...........\...\....\mydds.xco

................\...........\...\....\square_syn.v

................\...........\...\10-4

................\...........\...\....\coastas_dds.v

................\...........\...\....\costas_lf.v

................\...........\...\....\costas_loop.v

................\...........\...\....\costas_lpf.v

................\...........\...\....\costas_mult.v

................\...........\...\....\err_mult.v

................\...........\...\....\fir_lpf.xco

................\...........\...\....\mult.xco

................\...........\...\....\my_dds.xco

................\...........\...\10-6

................\...........\...\....\dearly_sub.v

................\...........\...\....\dedds.v

................\...........\...\....\delay_early_gate.v

................\...........\...\....\de_mult.xco

................\...........\...\....\eddds.xco

................\...........\...\....\iir.v

................\...........\...\....\iir1.v

................\...........\...

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