文件名称:Altera-SDRAM_controller-IP-CORE
介绍说明－－下载内容均来自于网络，请自行研究使用
ALTRA官方提供的SDRAM的控制内核，VHDL和VERILOG版本都有，希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Altera 官方SDRAM_controller IP CORE\sdr_sdram.pdf
...................................\verilog\doc\readme.txt
...................................\.......\...\sdr_sdram.pdf
...................................\.......\model\mt48lc8m16a2.v
...................................\.......\route\PLL1.v
...................................\.......\.....\sdr_sdram.csf
...................................\.......\.....\sdr_sdram.esf
...................................\.......\.....\sdr_sdram.vqm
...................................\.......\simulation\modelsim.ini
...................................\.......\..........\readme.txt
...................................\.......\..........\sdr_sdram_tb.v
...................................\.......\..........\work\altclklock\verilog.psm
...................................\.......\..........\....\..........\_primary.dat
...................................\.......\..........\....\..........\_primary.vhd
...................................\.......\..........\....\command\verilog.psm
...................................\.......\..........\....\.......\_primary.dat
...................................\.......\..........\....\.......\_primary.vhd
...................................\.......\..........\....\..ntrol_interface\verilog.psm
...................................\.......\..........\....\.................\_primary.dat
...................................\.......\..........\....\.................\_primary.vhd
...................................\.......\..........\....\mt48lc8m16a2\verilog.psm
...................................\.......\..........\....\............\_primary.dat
...................................\.......\..........\....\............\_primary.vhd
...................................\.......\..........\....\pll1\verilog.psm
...................................\.......\..........\....\....\_primary.dat
...................................\.......\..........\....\....\_primary.vhd
...................................\.......\..........\....\sdr_data_path\verilog.psm
...................................\.......\..........\....\.............\_primary.dat
...................................\.......\..........\....\.............\_primary.vhd
...................................\.......\..........\....\....sdram\verilog.psm
...................................\.......\..........\....\.........\_primary.dat
...................................\.......\..........\....\.........\_primary.vhd
...................................\.......\..........\....\........._tb\verilog.psm
...................................\.......\..........\....\............\_primary.dat
...................................\.......\..........\....\............\_primary.vhd
...................................\.......\..........\....\_info
...................................\.......\.ource\altclklock.v
...................................\.......\......\Command.v
...................................\.......\......\compile_all.v
...................................\.......\......\control_interface.v
...................................\.......\......\Params.v
...................................\.......\......\PLL1.v
...................................\.......\......\sdr_data_path.v
...................................\.......\......\sdr_sdram.v
...................................\.......\.ynthesis\synplicity\sdr_sdram.prj
...................................\.hdl\doc\readme.txt
...................................\....\...\sdr_sdram.pdf
...................................\....\model\io_utils.vhd
...................................\....\.....\mt48lc8m16a2.vhd
...................................\....\.....\mt48lc8m16a2.zip
...................................\....\.....\mti_pkg.vhd
...................................\....\.....\stdlogar.vhd
...................................\....\.....\util1164.vhd
...................................\....\route\pll1.vhd
...................................\....\.....\sdr_sdram.csf
...................................\....\.....\sdr_sdram.esf
...................................\....\.....\sdr_sdram.vqm
........