文件名称:RS_Encoder
介绍说明－－下载内容均来自于网络，请自行研究使用
具有16个校验位的RS编码器，在FPGA上实现。-With 16 RS encoder, the parity bit in the FPGA.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
RS_Encoder
..........\RS_Encoder.cmd_log
..........\RS_Encoder.ise
..........\RS_Encoder.lso
..........\RS_Encoder.ngc
..........\RS_Encoder.ngr
..........\RS_Encoder.ntrc_log
..........\RS_Encoder.prj
..........\RS_Encoder.restore
..........\RS_Encoder.stx
..........\RS_Encoder.syr
..........\RS_Encoder.v
..........\RS_Encoder.xst
..........\RS_Encoder_summary.html
..........\RS_Encoder_xdb
..........\..............\tmp
..........\RS_Encoder_xst.xrpt
..........\_xmsgs
..........\......\xst.xmsgs
..........\sysgen_wrapper.v
..........\tb_RS_Encoder.fdo
..........\tb_RS_Encoder.udo
..........\tb_RS_Encoder.v
..........\tb_RS_Encoder_wave.fdo
..........\testbench.v
..........\transcript
..........\vsim.wlf
..........\work
..........\....\@r@s_@encoder
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\.............\verilog.psm
..........\....\_info
..........\....\glbl
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\....\verilog.psm
..........\....\tb_@r@s_@encoder
..........\....\................\_primary.dat
..........\....\................\_primary.vhd
..........\....\................\verilog.psm
..........\xst
..........\...\dump.xst
..........\...\........\RS_Encoder.prj
..........\...\........\..............\ngx
..........\...\........\..............\...\notopt
..........\...\........\..............\...\opt
..........\...\........\..............\ntrc.scr
..........\...\projnav.tmp
..........\...\work
..........\...\....\hdllib.ref
..........\...\....\vlg48
..........\...\....\.....\_r_s___encoder.bin
..........\RS_Encoder.cmd_log
..........\RS_Encoder.ise
..........\RS_Encoder.lso
..........\RS_Encoder.ngc
..........\RS_Encoder.ngr
..........\RS_Encoder.ntrc_log
..........\RS_Encoder.prj
..........\RS_Encoder.restore
..........\RS_Encoder.stx
..........\RS_Encoder.syr
..........\RS_Encoder.v
..........\RS_Encoder.xst
..........\RS_Encoder_summary.html
..........\RS_Encoder_xdb
..........\..............\tmp
..........\RS_Encoder_xst.xrpt
..........\_xmsgs
..........\......\xst.xmsgs
..........\sysgen_wrapper.v
..........\tb_RS_Encoder.fdo
..........\tb_RS_Encoder.udo
..........\tb_RS_Encoder.v
..........\tb_RS_Encoder_wave.fdo
..........\testbench.v
..........\transcript
..........\vsim.wlf
..........\work
..........\....\@r@s_@encoder
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\.............\verilog.psm
..........\....\_info
..........\....\glbl
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\....\verilog.psm
..........\....\tb_@r@s_@encoder
..........\....\................\_primary.dat
..........\....\................\_primary.vhd
..........\....\................\verilog.psm
..........\xst
..........\...\dump.xst
..........\...\........\RS_Encoder.prj
..........\...\........\..............\ngx
..........\...\........\..............\...\notopt
..........\...\........\..............\...\opt
..........\...\........\..............\ntrc.scr
..........\...\projnav.tmp
..........\...\work
..........\...\....\hdllib.ref
..........\...\....\vlg48
..........\...\....\.....\_r_s___encoder.bin