文件名称:lab5

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  • VHDL编程
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  • [PDF]
  • 上传时间:
  • 2013-03-25
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  • 2.49mb
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  • 0次
  • 提 供 者:
  • shu***
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de2 altera 实验6 Adders, Subtractors, and Multipliers 答案-de2 altera experiment 5 Adders, Subtractors, and Multipliers answer
(系统自动生成,下载前可以参看下载内容)

下载文件列表





lab5\Lab 5.docx

....\Lab 5.pdf

....\part1\db\logic_util_heursitic.dat

....\.....\..\part1.amm.cdb

....\.....\..\part1.asm.qmsg

....\.....\..\part1.asm.rdb

....\.....\..\part1.asm_labs.ddb

....\.....\..\part1.cbx.xml

....\.....\..\part1.cmp.bpm

....\.....\..\part1.cmp.cdb

....\.....\..\part1.cmp.hdb

....\.....\..\part1.cmp.kpt

....\.....\..\part1.cmp.logdb

....\.....\..\part1.cmp.rdb

....\.....\..\part1.cmp0.ddb

....\.....\..\part1.cmp1.ddb

....\.....\..\part1.cmp_merge.kpt

....\.....\..\part1.db_info

....\.....\..\part1.eda.qmsg

....\.....\..\part1.fit.qmsg

....\.....\..\part1.hier_info

....\.....\..\part1.hif

....\.....\..\part1.idb.cdb

....\.....\..\part1.lpc.html

....\.....\..\part1.lpc.rdb

....\.....\..\part1.lpc.txt

....\.....\..\part1.map.bpm

....\.....\..\part1.map.cdb

....\.....\..\part1.map.hdb

....\.....\..\part1.map.kpt

....\.....\..\part1.map.logdb

....\.....\..\part1.map.qmsg

....\.....\..\part1.map_bb.cdb

....\.....\..\part1.map_bb.hdb

....\.....\..\part1.map_bb.logdb

....\.....\..\part1.pre_map.cdb

....\.....\..\part1.pre_map.hdb

....\.....\..\part1.root_partition.map.reg_db.cdb

....\.....\..\part1.rtlv.hdb

....\.....\..\part1.rtlv_sg.cdb

....\.....\..\part1.rtlv_sg_swap.cdb

....\.....\..\part1.sgdiff.cdb

....\.....\..\part1.sgdiff.hdb

....\.....\..\part1.sld_design_entry.sci

....\.....\..\part1.sld_design_entry_dsc.sci

....\.....\..\part1.smart_action.txt

....\.....\..\part1.sta.qmsg

....\.....\..\part1.sta.rdb

....\.....\..\part1.sta_cmp.6_slow.tdb

....\.....\..\part1.syn_hier_info

....\.....\..\part1.tis_db_list.ddb

....\.....\..\part1.tmw_info

....\.....\incremental_db\compiled_partitions\part1.db_info

....\.....\..............\...................\part1.root_partition.cmp.cdb

....\.....\..............\...................\part1.root_partition.cmp.dfp

....\.....\..............\...................\part1.root_partition.cmp.hdb

....\.....\..............\...................\part1.root_partition.cmp.kpt

....\.....\..............\...................\part1.root_partition.cmp.logdb

....\.....\..............\...................\part1.root_partition.cmp.rcfdb

....\.....\..............\...................\part1.root_partition.map.cdb

....\.....\..............\...................\part1.root_partition.map.dpi

....\.....\..............\...................\part1.root_partition.map.hbdb.cdb

....\.....\..............\...................\part1.root_partition.map.hbdb.hb_info

....\.....\..............\...................\part1.root_partition.map.hbdb.hdb

....\.....\..............\...................\part1.root_partition.map.hbdb.sig

....\.....\..............\...................\part1.root_partition.map.hdb

....\.....\..............\...................\part1.root_partition.map.kpt

....\.....\..............\README

....\.....\part1.asm.rpt

....\.....\part1.done

....\.....\part1.eda.rpt

....\.....\part1.fit.rpt

....\.....\part1.fit.summary

....\.....\part1.flow.rpt

....\.....\part1.jdi

....\.....\part1.map.rpt

....\.....\part1.map.summary

....\.....\part1.pin

....\.....\part1.pof

....\.....\part1.qpf

....\.....\part1.qsf

....\.....\part1.qsf.bak

....\.....\part1.sof

....\.....\part1.sta.rpt

....\.....\part1.sta.summary

....\.....\part1.v

....\.....\part1_nativelink_simulation.rpt

....\.....\simulation\modelsim\modelsim.ini

....\.....\..........\........\msim_transcript

....\.....\..........\........\part1.sft

....\.....\..........\........\part1.vho

....\.....\..........\........\part1_fast.vho

....\.....\..........\........\part1_modelsim.xrf

....\.....\..........\........\part1_run_msim_rtl_verilog.do

....\.....\..........\........\part1_run_msim_rtl_verilog.do.bak

....\.....\..........\........\part1_vhd.sdo

....\.....\..........\........\part1_vhd_fast.sdo

....\.....\..........\........\rtl_work\part1\verilog.prw

....\.....\..........\........\........\.....\verilog.psm

....\.....\..........\........\........\.....\_primary.dat

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