SDRAM\sdram.cr.mti

.....\sdram.mpf

.....\SDRAM_TOP.asm.rpt

.....\SDRAM_TOP.cdf

.....\SDRAM_TOP.done

.....\SDRAM_TOP.fit.rpt

.....\SDRAM_TOP.fit.smsg

.....\SDRAM_TOP.fit.summary

.....\SDRAM_TOP.flow.rpt

.....\SDRAM_TOP.jdi

.....\SDRAM_TOP.map.rpt

.....\SDRAM_TOP.map.smsg

.....\SDRAM_TOP.map.summary

.....\SDRAM_TOP.pin

.....\SDRAM_TOP.pof

.....\SDRAM_TOP.qpf

.....\SDRAM_TOP.qpf~

.....\SDRAM_TOP.qsf

.....\SDRAM_TOP.qsf~

.....\SDRAM_TOP.sof

.....\SDRAM_TOP.sta.rpt

.....\SDRAM_TOP.sta.summary

.....\SDRAM_TOP.tan.rpt

.....\SDRAM_TOP.tan.summary

.....\SDRAM_TOP_assignment_defaults.qdf

.....\SDRAM_TOP_description.txt

.....\SDRAM_WR_RD_SUCCESS.stp

.....\stp1.stp

.....\transcript

.....\vish_stacktrace.vstf

.....\vsim.wlf

.....\说明.txt

.....\详细设计方案\64MSDRAM.pdf

.....\............\HY57V641620.pdf

.....\............\标准SDR SDRAM控制器参考设计_an_lattice.pdf

.....\work\_info

.....\....\system\verilog.asm

.....\....\......\_primary.dat

.....\....\......\_primary.vhd

.....\....\.dr_top\verilog.asm

.....\....\.......\_primary.dat

.....\....\.......\_primary.vhd

.....\....\.....b\verilog.asm

.....\....\......\_primary.dat

.....\....\......\_primary.vhd

.....\....\....sig\verilog.asm

.....\....\.......\_primary.dat

.....\....\.......\_primary.vhd

.....\....\....data\verilog.asm

.....\....\........\_primary.dat

.....\....\........\_primary.vhd

.....\....\....ctrl\verilog.asm

.....\....\........\_primary.dat

.....\....\........\_primary.vhd

.....\....\...\verilog.asm

.....\....\...\_primary.dat

.....\....\...\_primary.vhd

.....\TB\BFM.v

.....\..\SDRAM.cr.mti

.....\..\SDRAM.mpf

.....\..\sdram.v

.....\..\sdr_ctrl.v

.....\..\sdr_data.v

.....\..\sdr_data.v~

.....\..\sdr_par.v

.....\..\sdr_sig.v

.....\..\sdr_tb.v

.....\..\sdr_top.v

.....\..\sdr_top.v~

.....\..\TB.v

.....\..\vsim.wlf

.....\..\仿真波形1.bmp

.....\..\仿真波形2.bmp

.....\..\work\_info

.....\..\....\sdr_top\verilog.asm

.....\..\....\.......\_primary.dat

.....\..\....\.......\_primary.vhd

.....\..\....\.....b\verilog.asm

.....\..\....\......\_primary.dat

.....\..\....\......\_primary.vhd

.....\..\....\....sig\verilog.asm

.....\..\....\.......\_primary.dat

.....\..\....\.......\_primary.vhd

.....\..\....\....data\verilog.asm

.....\..\....\........\_primary.dat

.....\..\....\........\_primary.vhd

.....\..\....\....ctrl\verilog.asm

.....\..\....\........\_primary.dat

.....\..\....\........\_primary.vhd

.....\..\....\...\verilog.asm

.....\..\....\...\_primary.dat

.....\..\....\...\_primary.vhd

.....\..\....\@t@b\verilog.asm

.....\..\....\....\_primary.dat

.....\..\....\....\_primary.vhd

.....\..\....\.b@f@m\verilog.asm

.....\..\....\......\_primary.dat

.....\..\....\......\_primary.vhd

.....\RTL\BFM.v

.....\...\BFM.v.bak