文件名称:lab5
- 所属分类：
- 嵌入式/单片机编程
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2014-05-07
- 文件大小：
- 15.37mb
- 下载次数：
- 0次
- 提 供 者：
- qinyu*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
用Xilinx内核生成器系统生成DCM内核
和存储器内核（ROM、RAM)等-DCM core and memory cores generated by Xilinx CORE Generator System (ROM, RAM), etc.
和存储器内核（ROM、RAM)等-DCM core and memory cores generated by Xilinx CORE Generator System (ROM, RAM), etc.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
lab5\data\ascii.coe
....\....\flower1_128x128.coe
....\....\flower2_128x128.coe
....\IPCore\IPCore.ipf
....\......\IPCore.ise
....\......\IPCore.ise_ISE_Backup
....\......\IPCore.ntrc_log
....\......\IPCore.restore
....\......\ipcore_top.bgn
....\......\ipcore_top.bit
....\......\IPCore_top.bld
....\......\IPCore_top.cmd_log
....\......\ipcore_top.drc
....\......\IPCore_top.lso
....\......\IPCore_top.ncd
....\......\IPCore_top.ngc
....\......\IPCore_top.ngd
....\......\IPCore_top.ngr
....\......\IPCore_top.pad
....\......\IPCore_top.par
....\......\IPCore_top.pcf
....\......\IPCore_top.prj
....\......\IPCore_top.stx
....\......\IPCore_top.syr
....\......\ipcore_top.twr
....\......\ipcore_top.twx
....\......\IPCore_top.unroutes
....\......\IPCore_top.ut
....\......\IPCore_top.xpi
....\......\IPCore_top.xst
....\......\IPCore_top_guide.ncd
....\......\IPCore_top_map.map
....\......\IPCore_top_map.mrp
....\......\IPCore_top_map.ncd
....\......\IPCore_top_map.ngm
....\......\IPCore_top_pad.csv
....\......\IPCore_top_pad.txt
....\......\IPCore_top_prev_built.ngd
....\......\IPCore_top_summary.html
....\......\IPCore_top_summary.xml
....\......\IPCore_top_usage.xml
....\......\PictureROM.asy
....\......\PictureROM.mif
....\......\PictureROM.ngc
....\......\PictureROM.sym
....\......\PictureROM.v
....\......\PictureROM.veo
....\......\PictureROM.vhd
....\......\PictureROM.vho
....\......\PictureROM.xco
....\......\PictureROM_flist.txt
....\......\PictureROM_readme.txt
....\......\PictureROM_xmdf.tcl
....\......\templates\coregen.xml
....\......\.mp\_cg\PictureROM.mif
....\......\transcript
....\......\VgaDCM.tfi
....\......\VgaDCM.v
....\......\VgaDCM.xaw
....\......\VgaDCM_arwz.ucf
....\......\xaw2verilog.log
....\......\.st\dump.xst\IPCore_top.prj\ntrc.scr
....\......\...\work\hdllib.ref
....\......\...\....\vlg0A\_picture_r_o_m.bin
....\......\...\....\...45\svga__ctrl.bin
....\......\...\....\....C\_i_p_core__top.bin
....\......\...\....\...62\_vga_d_c_m.bin
....\......\_impact.cmd
....\......\_impact.log
....\......\.ngo\netlist.lst
....\......\.xmsgs\bitgen.xmsgs
....\......\......\map.xmsgs
....\......\......\ngdbuild.xmsgs
....\......\......\par.xmsgs
....\......\......\trce.xmsgs
....\......\......\xst.xmsgs
....\sim\IPCoreSim.cr.mti
....\...\IPCoreSim.mpf
....\...\PictureROM.mif
....\...\rgb.rgb24
....\...\vsim.wlf
....\...\work\@i@p@core_svga_tb\verilog.asm
....\...\....\.................\_primary.dat
....\...\....\.................\_primary.vhd
....\...\....\..........top\verilog.asm
....\...\....\.............\_primary.dat
....\...\....\.............\_primary.vhd
....\...\....\.picture@r@o@m\verilog.asm
....\...\....\..............\_primary.dat
....\...\....\..............\_primary.vhd
....\...\....\.vga@d@c@m\verilog.asm
....\...\....\..........\_primary.dat
....\...\....\..........\_primary.vhd
....\...\....\svga_ctrl\verilog.asm
....\...\....\.........\_primary.dat
....\...\....\.........\_primary.vhd
....\...\....\_info
....\...\....\.opt\C
....\...\....\....\work_@i@p@core_svga_tb_fast.asm
....\...\....\....\work_@i@p@core_svga_tb_fast.dt2