文件名称:chuzhuche

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [Text]
  • 上传时间:
  • 2014-03-18
  • 文件大小:
  • 1.27mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • c*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

基于开发板制成的出租车计费器,适用于大学生的课程设计-Based development board made of taxi meter for college curriculum design
(系统自动生成,下载前可以参看下载内容)

下载文件列表





chuzhuche\FPGA_PROJECT1.PRJFPG

.........\FPGA_Project1.PrjFpgStructure

.........\FPGA_Project1.SO

.........\History\History.event

.........\LELEchongzuo.event

.........\ProjectOutputs\$$code$$.vhd

.........\..............\$$temp0.vhd

.........\..............\Default - All Constraints\AND2S.EDN

.........\..............\.........................\CDIV256DC50.EDN

.........\..............\.........................\Default - All Constraints.event

.........\..............\.........................\FPGA_PROJECT1.bfl

.........\..............\.........................\fpga_project1.bgn

.........\..............\.........................\fpga_project1.bit

.........\..............\.........................\fpga_project1.bld

.........\..............\.........................\FPGA_PROJECT1.edf

.........\..............\.........................\FPGA_PROJECT1.FlwCmp

.........\..............\.........................\FPGA_PROJECT1.mof

.........\..............\.........................\FPGA_PROJECT1.mpf

.........\..............\.........................\fpga_project1.ncd

.........\..............\.........................\fpga_project1.ngd

.........\..............\.........................\FPGA_PROJECT1.npl

.........\..............\.........................\fpga_project1.pad

.........\..............\.........................\fpga_project1.par

.........\..............\.........................\fpga_project1.rbt

.........\..............\.........................\fpga_project1.twr

.........\..............\.........................\FPGA_PROJECT1.ucf

.........\..............\.........................\fpga_project1.xpi

.........\..............\.........................\FPGA_PROJECT1_BUILD.UCF

.........\..............\.........................\fpga_project1_cclk.bgn

.........\..............\.........................\fpga_project1_cclk.bit

.........\..............\.........................\fpga_project1_cclk.rbt

.........\..............\.........................\FPGA_PROJECT1_CoreGen.txt

.........\..............\.........................\fpga_project1_map.mrp

.........\..............\.........................\fpga_project1_map.ncd

.........\..............\.........................\fpga_project1_map.ngm

.........\..............\.........................\fpga_project1_map.pcf

.........\..............\.........................\fpga_project1_pad.csv

.........\..............\.........................\fpga_project1_pad.txt

.........\..............\.........................\FPGA_PROJECT1_Synth.log

.........\..............\.........................\IOBUF8B.VHD

.........\..............\.........................\J16B_8B2.VHD

.........\..............\.........................\J8B_8S.VHD

.........\..............\.........................\LCD16X2A.EDN

.........\..............\.........................\Sheet1.VHD

.........\..............\.........................\Status Report.Txt

.........\..............\.........................\_blf\FPGA_PROJECT1_body.blf

.........\..............\.........................\....\FPGA_PROJECT1_header.blf

.........\..............\.........................\....\IOBUF8B_body.blf

.........\..............\.........................\....\IOBUF8B_header.blf

.........\..............\.........................\....\JFQLCD_body.blf

.........\..............\.........................\....\JFQLCD_header.blf

.........\..............\.........................\....\JFQZMK_body.blf

.........\..............\.........................\....\JFQZMK_header.blf

.........\..............\.........................\....\LessThan_32u_32u_body.blf

.........\..............\.........................\....\LessThan_32u_32u_header.blf

.........\..............\.........................\....\_blf.event

.........\..............\.........................\.ngo\AND2S.ngo

.........\..............\.........................\....\CDIV256DC50.ngo

.........\..............\.........................\....\fpga_project1.ngo

.........\..............\.........................\....\LCD16X2A.ngo

.........\..............\.........................\....\netlist.lst

.........\........

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 本站是交换下载平台,提供交流渠道,下载内容来自于网络,除下载问题外,其它问题请自行百度更多...
  • 请直接用浏览器下载本站内容,不要使用迅雷之类的下载软件,用WinRAR最新版进行解压.
  • 如果您发现内容无法下载,请稍后再次尝试;或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎,请到消费记录里找到下载记录反馈给我们,经确认后退回积分.
  • 如下载前有疑问,可以通过点击"提供者"的名字,查看对方的联系方式,联系对方咨询.

相关评论

暂无评论内容.

发表评论

*主  题:
*内  容:
*验 证 码:

源码中国 www.ymcn.org