文件名称:qiangdaqi
介绍说明－－下载内容均来自于网络，请自行研究使用
基本功能：
1. 八路抢答器，同时供8个选手参赛，编号分别为1到8。每位选手用一个答题按钮和LED灯，选手按下时其灯亮。
2. 给主持人一个控制开关，实现系统的复位、抢答开始和分数清零。
3. 具有数据锁存和显示功能。抢答开始后，如果有选手按下了抢答按钮，其编号立即锁存并显示在LCD液晶显示屏上。此外，禁止其他选手再次抢答。选手的编号一直会保存，直到主持人清除。
-Basic features: 1. Eight Responder, while for eight contestants, numbered 1-8. Each player with an answer button and LED lights, when the players pressed their lights. 2. to host a control switch, reset the system to achieve, the answer began and scores cleared. 3. With the data latch and display functions. After the answer begins, if there are players pressed the answer button, its number immediately latched and displayed on the LCD screen. Furthermore, against other players answer again. Number of players have been saved until the host clears.
1. 八路抢答器，同时供8个选手参赛，编号分别为1到8。每位选手用一个答题按钮和LED灯，选手按下时其灯亮。
2. 给主持人一个控制开关，实现系统的复位、抢答开始和分数清零。
3. 具有数据锁存和显示功能。抢答开始后，如果有选手按下了抢答按钮，其编号立即锁存并显示在LCD液晶显示屏上。此外，禁止其他选手再次抢答。选手的编号一直会保存，直到主持人清除。
-Basic features: 1. Eight Responder, while for eight contestants, numbered 1-8. Each player with an answer button and LED lights, when the players pressed their lights. 2. to host a control switch, reset the system to achieve, the answer began and scores cleared. 3. With the data latch and display functions. After the answer begins, if there are players pressed the answer button, its number immediately latched and displayed on the LCD screen. Furthermore, against other players answer again. Number of players have been saved until the host clears.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
MY抢答器\FPGA_Project1.PrjFpg
........\FPGA_Project1.PrjFpgStructure
........\History\FPGA_Project1.~(1).PrjFpg.Zip
........\.......\FPGA_Project1.~(2).PrjFpg.Zip
........\.......\FPGA_Project1.~(3).PrjFpg.Zip
........\.......\jishi.~(1).SchLib.Zip
........\.......\Sheet3.~(1).SchDoc.Zip
........\.......\Sheet3.~(2).SchDoc.Zip
........\.......\Sheet3.~(3).SchDoc.Zip
........\.......\VHDL2.~(1).Vhd.Zip
........\.......\VHDL2.~(2).Vhd.Zip
........\.......\VHDL2.~(3).Vhd.Zip
........\.......\VHDL3.~(1).Vhd.Zip
........\jianbie.SchLib
........\jifen.SchLib
........\jishi.SchLib
........\key_scan.SchLib
........\lcd_scan.SchLib
........\Project Logs for FPGA_Project1\Sheet3 SCH ECO 2013-6-7 12-24-28.LOG
........\..............................\Sheet3 SCH ECO 2013-6-7 12-36-32.LOG
........\.......Outputs\Sheet3.VHD
........\..............\Status Report.Txt
........\..............\__Previews\Sheet3.VHDPreview
........\Sheet3.SchDoc
........\suocun.SchLib
........\VHDL1.Vhd
........\VHDL2.Vhd
........\VHDL3.Vhd
........\VHDL4.Vhd
........\VHDL5.Vhd
........\VHDL6.Vhd
........\VHDL7.Vhd
........\VHDL8.Vhd
........\voice.SchLib
........\zubieshuchu.SchLib
........\__Previews\Sheet3.SchDocPreview
........\..........\VHDL1.VhdPreview
........\..........\VHDL2.VhdPreview
........\..........\VHDL3.VhdPreview
........\..........\VHDL4.VhdPreview
........\..........\VHDL5.VhdPreview
........\..........\VHDL6.VhdPreview
........\..........\VHDL7.VhdPreview
........\..........\VHDL8.VhdPreview
........\控制和计分模块的波形仿真\FPGA_Project2.PrjFpg
........\........................\FPGA_Project2.SO
........\........................\FPGA_Project5.PrjFpg
........\........................\FPGA_Project5.SO
........\........................\Test_aaa.VHDTST
........\........................\Test_jf.VHDTST
........\........................\VHDL1.Vhd
........\........................\VHDL4.Vhd
........\........................\__Previews\VHDL1.VhdPreview
........\锁存和计时的波形图仿真\FPGA_Project1.PrjFpg
........\......................\FPGA_Project1.SO
........\......................\FPGA_Project2.PrjFpg
........\......................\FPGA_Project2.SO
........\......................\History\FPGA_Project1.~(1).PrjFpg.Zip
........\......................\.......\FPGA_Project1.~(2).PrjFpg.Zip
........\......................\.......\FPGA_Project1.~(3).PrjFpg.Zip
........\......................\.......\FPGA_Project1.~(4).PrjFpg.Zip
........\......................\.......\FPGA_Project1.~(5).PrjFpg.Zip
........\......................\.......\FPGA_Project1.~(6).PrjFpg.Zip
........\......................\.......\FPGA_Project2.~(1).PrjFpg.Zip
........\......................\.......\FPGA_Project2.~(1).SO.Zip
........\......................\.......\FPGA_Project2.~(10).PrjFpg.Zip
........\......................\.......\FPGA_Project2.~(2).SO.Zip
........\......................\.......\FPGA_Project2.~(3).SO.Zip
........\......................\.......\FPGA_Project2.~(4).PrjFpg.Zip
........\......................\.......\FPGA_Project2.~(5).PrjFpg.Zip
........\......................\.......\FPGA_Project2.~(6).PrjFpg.Zip
........\......................\.......\FPGA_Project2.~(7).PrjFpg.Zip
........\......................\.......\FPGA_Project2.~(8).PrjFpg.Zip
........\......................\.......\FPGA_Project2.~(9).PrjFpg.Zip
........\......................\.......\Test_suocun.~(1).VHDTST.Zip
........\......................\.......\Test_suocun.~(2).VHDTST.Zip
........\......................\.......\Test_suocun.~(3).VHDTST.Zip
........\......................\.......\VHDL1.~(1).Vhd.Zip
........\......................\.......\VHDL1.~(10).Vhd.Zip
........\......................\.......\VHDL1.~(11).Vhd.Zip
........\......................\.......\VHDL1.~(12).Vhd.Zip
........\......................\.......\VHDL1.~(13).Vhd.Zip
........\......................\.......\VHDL1.~(14).Vhd.Zip
........\......................\.......\VHDL1.~(15).Vhd.Zip
........\......................\.......\VHDL1.~(16).Vhd.Zip
........\......................\.......\VHDL1.~(6).Vhd.Zip
......