文件名称:20161122_ff
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MD5认证部分的第一轮中包含F函数的一次操作的FPGA实现源代码，采用Verilog，在Quartus II上综合-MD5 authentication part of the first round contains an F function of the operation of the FPGA implementation of the source code, using Verilog, integrated in the Quartus II
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下载文件列表
20161122_ff\db\ff.cbx.xml
...........\..\ff.cmp.rdb
...........\..\ff.cmp_merge.kpt
...........\..\ff.db_info
...........\..\ff.eda.qmsg
...........\..\ff.hier_info
...........\..\ff.hif
...........\..\ff.lpc.html
...........\..\ff.lpc.rdb
...........\..\ff.lpc.txt
...........\..\ff.map.bpm
...........\..\ff.map.cdb
...........\..\ff.map.hdb
...........\..\ff.map.kpt
...........\..\ff.map.logdb
...........\..\ff.map.qmsg
...........\..\ff.map.rdb
...........\..\ff.map_bb.cdb
...........\..\ff.map_bb.hdb
...........\..\ff.map_bb.logdb
...........\..\ff.pre_map.cdb
...........\..\ff.pre_map.hdb
...........\..\ff.root_partition.map.reg_db.cdb
...........\..\ff.rtlv.hdb
...........\..\ff.rtlv_sg.cdb
...........\..\ff.rtlv_sg_swap.cdb
...........\..\ff.sgdiff.cdb
...........\..\ff.sgdiff.hdb
...........\..\ff.sld_design_entry.sci
...........\..\ff.sld_design_entry_dsc.sci
...........\..\ff.smart_action.txt
...........\..\ff.syn_hier_info
...........\..\ff.tis_db_list.ddb
...........\..\ff.tmw_info
...........\..\logic_util_heursitic.dat
...........\..\prev_cmp_ff.qmsg
...........\ff.done
...........\ff.eda.rpt
...........\ff.flow.rpt
...........\ff.map.rpt
...........\ff.map.summary
...........\ff.qpf
...........\ff.qsf
...........\ff.qws
...........\ff.v
...........\ff.v.bak
...........\ff_nativelink_simulation.rpt
...........\incremental_db\compiled_partitions\ff.db_info
...........\..............\...................\ff.root_partition.map.cdb
...........\..............\...................\ff.root_partition.map.dpi
...........\..............\...................\ff.root_partition.map.hbdb.cdb
...........\..............\...................\ff.root_partition.map.hbdb.hb_info
...........\..............\...................\ff.root_partition.map.hbdb.hdb
...........\..............\...................\ff.root_partition.map.hbdb.sig
...........\..............\...................\ff.root_partition.map.hdb
...........\..............\...................\ff.root_partition.map.kpt
...........\..............\README
...........\simulation\modelsim\ff.vt
...........\..........\........\ff.vt.bak
...........\..........\........\ff_run_msim_rtl_verilog.do
...........\..........\........\ff_run_msim_rtl_verilog.do.bak
...........\..........\........\ff_run_msim_rtl_verilog.do.bak1
...........\..........\........\ff_run_msim_rtl_verilog.do.bak10
...........\..........\........\ff_run_msim_rtl_verilog.do.bak2
...........\..........\........\ff_run_msim_rtl_verilog.do.bak3
...........\..........\........\ff_run_msim_rtl_verilog.do.bak4
...........\..........\........\ff_run_msim_rtl_verilog.do.bak5
...........\..........\........\ff_run_msim_rtl_verilog.do.bak6
...........\..........\........\ff_run_msim_rtl_verilog.do.bak7
...........\..........\........\ff_run_msim_rtl_verilog.do.bak8
...........\..........\........\ff_run_msim_rtl_verilog.do.bak9
...........\..........\........\modelsim.ini
...........\..........\........\msim_transcript
...........\..........\........\rtl_work\ff\verilog.prw
...........\..........\........\........\..\verilog.psm
...........\..........\........\........\..\_primary.dat
...........\..........\........\........\..\_primary.dbs
...........\..........\........\........\..\_primary.vhd
...........\..........\........\........\.._vlg_tst\verilog.prw
...........\..........\........\........\..........\verilog.psm
...........\..........\........\........\..........\_primary.dat
...........\..........\........\........\..........\_primary.dbs
...........\..........\........\........\..........\_primary.vhd
...........\..........\........\........\_info
...........\..........\........\........\_vmake
...........\..........\........\vsim.wlf
...........\..........\........\rtl_work\ff
...........\..........\........\........\ff_vlg_tst
...........\..........\........\........\_temp
...........\..........\........\rtl_work
...........\incremental_db\compiled_partitions
...........\simulation\modelsim
...........\db
...........\incremental_db
...........\simulation
20161122_ff