文件名称:08-1_VGA_Display_Test_640480

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2016-07-08
  • 文件大小:
  • 142kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 郑**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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基于quartusII开发环境的VGA视频通信程序,很好的资料,欢迎下载-Based on quartusII development environment of VGA video communication program, very good information, welcome to download
(系统自动生成,下载前可以参看下载内容)

下载文件列表





08-1_VGA_Display_Test_640480\dev\output_files\greybox_tmp\cbx_args.txt

............................\...\............\sys_pll.qip

............................\...\............\VGA_Display_Test.asm.rpt

............................\...\............\VGA_Display_Test.cdf

............................\...\............\VGA_Display_Test.done

............................\...\............\VGA_Display_Test.fit.rpt

............................\...\............\VGA_Display_Test.fit.smsg

............................\...\............\VGA_Display_Test.fit.summary

............................\...\............\VGA_Display_Test.flow.rpt

............................\...\............\VGA_Display_Test.jdi

............................\...\............\VGA_Display_Test.map.rpt

............................\...\............\VGA_Display_Test.map.summary

............................\...\............\VGA_Display_Test.pin

............................\...\............\VGA_Display_Test.pof

............................\...\............\VGA_Display_Test.sof

............................\...\............\VGA_Display_Test.sta.rpt

............................\...\............\VGA_Display_Test.sta.summary

............................\...\PLLJ_PLLSPE_INFO.txt

............................\...\sys_pll.qip

............................\...\VGA_Display_Test.pti_db_list.ddb

............................\...\VGA_Display_Test.qpf

............................\...\VGA_Display_Test.qsf

............................\...\VGA_Display_Test.qws

............................\...\VGA_Display_Test.tis_db_list.ddb

............................\...\VIP_System.sdc

............................\...\VIP_System.sdc.bak

............................\sim\VGA_Display_TB\lcd_24bit_ip\lcd_display.v

............................\...\..............\............\lcd_display.v.bak

............................\...\..............\............\lcd_driver.v

............................\...\..............\............\lcd_driver.v.bak

............................\...\..............\............\lcd_driver_zoom.v

............................\...\..............\............\lcd_driver_zoom.v.bak

............................\...\..............\............\lcd_para.v

............................\...\..............\............\lcd_para.v.bak

............................\...\..............\tcl_stacktrace.txt

............................\...\..............\transcript

............................\...\..............\VGA_Display_TB.cr.mti

............................\...\..............\VGA_Display_TB.mpf

............................\...\..............\VGA_Display_TB.v

............................\...\..............\vsim.wlf

............................\...\..............\wave.do

............................\...\..............\.ork\@l@c@d_@display_@t@b\verilog.prw

............................\...\..............\....\....................\verilog.psm

............................\...\..............\....\....................\_primary.dat

............................\...\..............\....\....................\_primary.dbs

............................\...\..............\....\....................\_primary.vhd

............................\...\..............\....\lcd_display\verilog.prw

............................\...\..............\....\...........\verilog.psm

............................\...\..............\....\...........\_primary.dat

............................\...\..............\....\...........\_primary.dbs

............................\...\..............\....\...........\_primary.vhd

............................\...\..............\....\.....river\verilog.prw

............................\...\..............\....\..........\verilog.psm

............................\...\..............\....\..........\_primary.dat

............................\...\..............\....\..........\_primary.dbs

............................\...\..............\....\..........\_primary.vhd

............................\...\..............\....\_info

............................\...\..............\....\.temp\vlog2gz5id

........................

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