文件名称:09_SDRAM_VGA_Display_Test640480
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在quartusII的开发环境下，编写的VerilogHDL语言的SDRAM通信程序，欢迎下载，这是基于Crazybingo的板卡环境设计-Under the development environment of quartusII, write SDRAM VerilogHDL language communication program, welcome to download, this is based on Crazybingo board environment design
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下载文件列表
09_SDRAM_VGA_Display_Test640480\core\sdram_pll.bsf
...............................\....\sdram_pll.ppf
...............................\....\sdram_pll.qip
...............................\....\sdram_pll.v
...............................\dev\output_files\greybox_tmp\cbx_args.txt
...............................\...\............\read_fifo1.qip
...............................\...\............\SDRAM_VGA_Display_Test.asm.rpt
...............................\...\............\SDRAM_VGA_Display_Test.cdf
...............................\...\............\SDRAM_VGA_Display_Test.done
...............................\...\............\SDRAM_VGA_Display_Test.fit.rpt
...............................\...\............\SDRAM_VGA_Display_Test.fit.smsg
...............................\...\............\SDRAM_VGA_Display_Test.fit.summary
...............................\...\............\SDRAM_VGA_Display_Test.flow.rpt
...............................\...\............\SDRAM_VGA_Display_Test.jdi
...............................\...\............\SDRAM_VGA_Display_Test.map.rpt
...............................\...\............\SDRAM_VGA_Display_Test.map.smsg
...............................\...\............\SDRAM_VGA_Display_Test.map.summary
...............................\...\............\SDRAM_VGA_Display_Test.pin
...............................\...\............\SDRAM_VGA_Display_Test.sof
...............................\...\............\SDRAM_VGA_Display_Test.sta.rpt
...............................\...\............\SDRAM_VGA_Display_Test.sta.summary
...............................\...\............\sys_pll.qip
...............................\...\............\write_fifo1.qip
...............................\...\PLLJ_PLLSPE_INFO.txt
...............................\...\read_fifo1.qip
...............................\...\SDRAM_VGA_Display_Test.qpf
...............................\...\SDRAM_VGA_Display_Test.qsf
...............................\...\SDRAM_VGA_Display_Test.qws
...............................\...\SDRAM_VGA_Display_Test.tcl
...............................\...\SDRAM_VGA_Display_Test.tcl.bak
...............................\...\sys_pll.qip
...............................\...\VIP_System.sdc
...............................\...\VIP_System.sdc.bak
...............................\src\Camera_ISP_Design.v.bak
...............................\...\lcd_24bit_ip\lcd_display.v
...............................\...\............\lcd_display.v.bak
...............................\...\............\lcd_driver.v
...............................\...\............\lcd_driver.v.bak
...............................\...\............\lcd_driver_zoom.v
...............................\...\............\lcd_driver_zoom.v.bak
...............................\...\............\lcd_para.v
...............................\...\............\lcd_para.v.bak
...............................\...\............\read_fifo1.qip
...............................\...\............\sys_pll.qip
...............................\...\............\VGAData_Simulate_24Bit.v
...............................\...\............\VGAData_Simulate_24Bit.v.bak
...............................\...\............\write_fifo1.qip
...............................\...\Sdram_Control_2Port_1MX32Bit\command.v
...............................\...\............................\command.v.bak
...............................\...\............................\control_interface.v
...............................\...\............................\control_interface.v.bak
...............................\...\............................\read_fifo1.bsf
...............................\...\............................\read_fifo1.qip
...............................\...\............................\read_fifo1.v
...............................\...\............................\read_fifo1.v.bak
...............................\...\............................\read_fifo1_wave0.jpg
...............................\...\............................\read_fifo1_waveforms.html
...............................\...\............................\Sdram_Control_2Port.v
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