文件名称:5_Gray_Mean_Filter
介绍说明－－下载内容均来自于网络，请自行研究使用
均值滤波是典型的线性滤波算法，（Verilog HDL）设计所需的模块有：
（1）带PLL的全局时钟管理模块 system_ctrl_pll.v
（2）OV7725 COMS Sensor的初始化模块 i2c_timing_ctrl、I2C_OV7725_RGB565_Conofig
（3）OV7725 COMS Sensor的视频信号采集模块COMS_Capture_RGB565
（4）SDRAM数据交互控制器Sdram_Control_2Port
（5）VGA时序驱动电路lcd_driver
-Design the required modules are:
(1) global with PLL clock management module system_ctrl_pll. V.
(2) the OV7725 COMS i2c_timing_ctrl initialization module, I2C_OV7725_RGB565_Conofig Sensor
(3) the OV7725 COMS Sensor COMS_Capture_RGB565 video signal acquisition module
(4) SDRAM controller data interaction Sdram_Control_2Port
(5) the VGA timing drive circuit lcd_driver
逐句翻译
（1）带PLL的全局时钟管理模块 system_ctrl_pll.v
（2）OV7725 COMS Sensor的初始化模块 i2c_timing_ctrl、I2C_OV7725_RGB565_Conofig
（3）OV7725 COMS Sensor的视频信号采集模块COMS_Capture_RGB565
（4）SDRAM数据交互控制器Sdram_Control_2Port
（5）VGA时序驱动电路lcd_driver
-Design the required modules are:
(1) global with PLL clock management module system_ctrl_pll. V.
(2) the OV7725 COMS i2c_timing_ctrl initialization module, I2C_OV7725_RGB565_Conofig Sensor
(3) the OV7725 COMS Sensor COMS_Capture_RGB565 video signal acquisition module
(4) SDRAM controller data interaction Sdram_Control_2Port
(5) the VGA timing drive circuit lcd_driver
逐句翻译
(系统自动生成,下载前可以参看下载内容)
下载文件列表
5_Gray_Mean_Filter
..................\core
..................\....\VGA_Char_Display_Test.pti_db_list.ddb
..................\....\VGA_Char_Display_Test.tis_db_list.ddb
..................\....\crazybingo.TXT
..................\....\crazybingo.mif
..................\....\greybox_tmp
..................\....\...........\cbx_args.txt
..................\....\hello_world.TXT
..................\....\hello_world.mif
..................\....\sys_pll.qip
..................\....\vip_rom1.qip
..................\....\vip_rom1.v
..................\....\vip_rom2.qip
..................\....\vip_rom2.v
..................\....\vip_rom2_bb.v
..................\dev
..................\...\CMOS_VIP_HDL_Demo.qpf
..................\...\CMOS_VIP_HDL_Demo.qsf
..................\...\CMOS_VIP_HDL_Demo.qws
..................\...\PLLJ_PLLSPE_INFO.txt
..................\...\VIP_System.sdc
..................\...\db
..................\...\..\CMOS_VIP_HDL_Demo.asm.qmsg
..................\...\..\CMOS_VIP_HDL_Demo.asm.rdb
..................\...\..\CMOS_VIP_HDL_Demo.asm_labs.ddb
..................\...\..\CMOS_VIP_HDL_Demo.cbx.xml
..................\...\..\CMOS_VIP_HDL_Demo.cmp.bpm
..................\...\..\CMOS_VIP_HDL_Demo.cmp.cdb
..................\...\..\CMOS_VIP_HDL_Demo.cmp.hdb
..................\...\..\CMOS_VIP_HDL_Demo.cmp.idb
..................\...\..\CMOS_VIP_HDL_Demo.cmp.kpt
..................\...\..\CMOS_VIP_HDL_Demo.cmp.logdb
..................\...\..\CMOS_VIP_HDL_Demo.cmp.rdb
..................\...\..\CMOS_VIP_HDL_Demo.cmp_merge.kpt
..................\...\..\CMOS_VIP_HDL_Demo.cycloneive_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
..................\...\..\CMOS_VIP_HDL_Demo.cycloneive_io_sim_cache.31um_ss_1200mv_0c_slow.hsd
..................\...\..\CMOS_VIP_HDL_Demo.cycloneive_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
..................\...\..\CMOS_VIP_HDL_Demo.db_info
..................\...\..\CMOS_VIP_HDL_Demo.fit.qmsg
..................\...\..\CMOS_VIP_HDL_Demo.hier_info
..................\...\..\CMOS_VIP_HDL_Demo.hif
..................\...\..\CMOS_VIP_HDL_Demo.ipinfo
..................\...\..\CMOS_VIP_HDL_Demo.lpc.html
..................\...\..\CMOS_VIP_HDL_Demo.lpc.rdb
..................\...\..\CMOS_VIP_HDL_Demo.lpc.txt
..................\...\..\CMOS_VIP_HDL_Demo.map.ammdb
..................\...\..\CMOS_VIP_HDL_Demo.map.bpm
..................\...\..\CMOS_VIP_HDL_Demo.map.cdb
..................\...\..\CMOS_VIP_HDL_Demo.map.hdb
..................\...\..\CMOS_VIP_HDL_Demo.map.kpt
..................\...\..\CMOS_VIP_HDL_Demo.map.logdb
..................\...\..\CMOS_VIP_HDL_Demo.map.qmsg
..................\...\..\CMOS_VIP_HDL_Demo.map.rdb
..................\...\..\CMOS_VIP_HDL_Demo.map_bb.cdb
..................\...\..\CMOS_VIP_HDL_Demo.map_bb.hdb
..................\...\..\CMOS_VIP_HDL_Demo.map_bb.logdb
..................\...\..\CMOS_VIP_HDL_Demo.pre_map.hdb
..................\...\..\CMOS_VIP_HDL_Demo.pti_db_list.ddb
..................\...\..\CMOS_VIP_HDL_Demo.root_partition.map.reg_db.cdb
..................\...\..\CMOS_VIP_HDL_Demo.routing.rdb
..................\...\..\CMOS_VIP_HDL_Demo.rpp.qmsg
..................\...\..\CMOS_VIP_HDL_Demo.rtlv.hdb
..................\...\..\CMOS_VIP_HDL_Demo.rtlv_sg.cdb
..................\...\..\CMOS_VIP_HDL_Demo.rtlv_sg_swap.cdb
..................\...\..\CMOS_VIP_HDL_Demo.sgate.rvd
..................\...\..\CMOS_VIP_HDL_Demo.sgate_sm.rvd
..................\...\..\CMOS_VIP_HDL_Demo.sgdiff.cdb
..................\...\..\CMOS_VIP_HDL_Demo.sgdiff.hdb
..................\...\..\CMOS_VIP_HDL_Demo.sld_design_entry.sci
..................\...\..\CMOS_VIP_HDL_Demo.sld_design_entry_dsc.sci
..................\...\..\CMOS_VIP_HDL_Demo.smart_action.txt
..................\...\..\CMOS_VIP_HDL_Demo.sta.qmsg
..................\...\..\CMOS_VIP_HDL_Demo.sta.rdb
..................\...\..\CMOS_VIP_HDL_Demo.sta_cmp.8_slow_1200mv_85c.tdb
..................\...\..\CMOS_VIP_HDL_Demo.syn_hier_info
..................\...\..\CMOS_VIP_HDL_Demo.tis_db_list.ddb
..................\...\..\CMOS_VIP_HDL_Demo.tiscmp.fast_1200mv_0c.ddb
..................\