文件名称:dianti
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实现电梯的相关控制系统，在开发板EGO1上实现，数码管显示相关的楼层和状态-dianti in verilog
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下载文件列表
dianti
......\.Xil
......\shiyan44dianti.cache
......\....................\compile_simlib
......\....................\..............\activehdl
......\....................\..............\ies
......\....................\..............\modelsim
......\....................\..............\questa
......\....................\..............\riviera
......\....................\..............\vcs
......\....................\wt
......\....................\..\java_command_handlers.wdf
......\....................\..\project.wpc
......\....................\..\synthesis.wdf
......\....................\..\synthesis_details.wdf
......\....................\..\webtalk_pa.xml
......\....................\..\xsim.wdf
......\shiyan44dianti.hw
......\.................\hw_1
......\.................\....\hw.xml
......\.................\....\wave
......\.................\shiyan44dianti.lpr
......\shiyan44dianti.ip_user_files
......\............................\ipstatic
......\............................\README.txt
......\shiyan44dianti.runs
......\...................\.jobs
......\...................\.....\vrs_config_1.xml
......\...................\.....\vrs_config_10.xml
......\...................\.....\vrs_config_11.xml
......\...................\.....\vrs_config_12.xml
......\...................\.....\vrs_config_13.xml
......\...................\.....\vrs_config_14.xml
......\...................\.....\vrs_config_15.xml
......\...................\.....\vrs_config_16.xml
......\...................\.....\vrs_config_17.xml
......\...................\.....\vrs_config_18.xml
......\...................\.....\vrs_config_19.xml
......\...................\.....\vrs_config_2.xml
......\...................\.....\vrs_config_20.xml
......\...................\.....\vrs_config_21.xml
......\...................\.....\vrs_config_22.xml
......\...................\.....\vrs_config_23.xml
......\...................\.....\vrs_config_24.xml
......\...................\.....\vrs_config_25.xml
......\...................\.....\vrs_config_3.xml
......\...................\.....\vrs_config_4.xml
......\...................\.....\vrs_config_5.xml
......\...................\.....\vrs_config_6.xml
......\...................\.....\vrs_config_7.xml
......\...................\.....\vrs_config_8.xml
......\...................\.....\vrs_config_9.xml
......\...................\impl_1
......\...................\......\.init_design.begin.rst
......\...................\......\.init_design.end.rst
......\...................\......\.opt_design.begin.rst
......\...................\......\.opt_design.end.rst
......\...................\......\.place_design.begin.rst
......\...................\......\.place_design.end.rst
......\...................\......\.route_design.begin.rst
......\...................\......\.route_design.end.rst
......\...................\......\.vivado.begin.rst
......\...................\......\.vivado.end.rst
......\...................\......\.Vivado_Implementation.queue.rst
......\...................\......\.write_bitstream.begin.rst
......\...................\......\.write_bitstream.end.rst
......\...................\......\.Xil
......\...................\......\gen_run.xml
......\...................\......\htr.txt
......\...................\......\init_design.pb
......\...................\......\ISEWrap.js
......\...................\......\ISEWrap.sh
......\...................\......\opt_design.pb
......\...................\......\place_design.pb
......\...................\......\project.wdf
......\...................\......\route_design.pb
......\...................\......\rundef.js
......\...................\......\runme.bat
......\...................\......\runme.log
......\...................\......\runme.sh
......\...................\......\top.bit
......\...................\......\top.tcl
......\...................\......\top.vdi
......\...................\......\top_11092.backup.vdi
......\...................\......\top_14068.backup.vdi
......\...................\......\top_4408.backup.vdi
......\...................\......\top_clock_utilization_routed.r