文件名称:PROJECT4

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  • 嵌入式/单片机编程
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  • 上传时间:
  • 2018-04-12
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  • 2.85mb
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  • 沉**
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设计一个简易数字信号传输性能分析仪,实现数字信号传输性能测试;同时,设计三个低通滤波器和一个伪随机信号发生器用来模拟传输信道。(A simple digital signal transmission performance analyzer is designed to test the transmission performance of the digital signal. At the same time, three low-pass filters and a pseudo-random signal generator are designed to simulate the transmission channel.)
相关搜索: fpga
数字信号发生器

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下载文件列表

文件名大小更新时间
2011全国大学生电子设计题目.pdf 133096 2013-04-06
m\modelsim\M.cr.mti 521 2014-03-10
m\modelsim\M.mpf 55143 2014-03-10
m\modelsim\testbench.cr.mti 519 2015-09-13
m\modelsim\testbench.mpf 55143 2015-09-13
m\modelsim\vsim.wlf 40960 2015-09-13
m\modelsim\work\@digital@signal@gen\verilog.asm 6608 2015-09-13
m\modelsim\work\@digital@signal@gen\verilog.rw 1900 2015-09-13
m\modelsim\work\@digital@signal@gen\_primary.dat 766 2015-09-13
m\modelsim\work\@digital@signal@gen\_primary.dbs 2453 2015-09-13
m\modelsim\work\@digital@signal@gen\_primary.vhd 384 2015-09-13
m\modelsim\work\@_opt\vopt3rjhvd 1720 2014-03-10
m\modelsim\work\@_opt\vopt6rvdbi 384 2014-03-10
m\modelsim\work\@_opt\vopta8habi 2806 2014-03-10
m\modelsim\work\@_opt\vopta90dtd 78 2014-03-10
m\modelsim\work\@_opt\voptdr67bi 850 2014-03-10
m\modelsim\work\@_opt\voptesm9td 844 2014-03-10
m\modelsim\work\@_opt\vopth9b6td 457 2014-03-10
m\modelsim\work\@_opt\vopthr04vg 416 2014-03-10
m\modelsim\work\@_opt\voptm8n0vg 845 2014-03-10
m\modelsim\work\@_opt\voptms03td 516 2014-03-10
m\modelsim\work\@_opt\voptz7ykvd 376 2014-03-10
m\modelsim\work\@_opt\_deps 1180 2014-03-10
m\modelsim\work\@_opt1\vopt1cigfk 1720 2015-09-13
m\modelsim\work\@_opt1\vopt5agdmh 384 2015-09-13
m\modelsim\work\@_opt1\vopt9t5amh 2453 2015-09-13
m\modelsim\work\@_opt1\voptf9f1nh 766 2015-09-13
m\modelsim\work\@_opt1\voptjs4xmh 416 2015-09-13
m\modelsim\work\@_opt1\voptjttvgk 78 2015-09-13
m\modelsim\work\@_opt1\voptnagrgk 844 2015-09-13
m\modelsim\work\@_opt1\voptq9ttmh 939 2015-09-13
m\modelsim\work\@_opt1\vopttt5kgk 457 2015-09-13
m\modelsim\work\@_opt1\voptxavhgk 516 2015-09-13
m\modelsim\work\@_opt1\voptyvwkfk 376 2015-09-13
m\modelsim\work\@_opt1\_deps 1180 2015-09-13
m\modelsim\work\testbench\verilog.asm 4784 2015-09-13
m\modelsim\work\testbench\verilog.rw 1648 2015-09-13
m\modelsim\work\testbench\_primary.dat 457 2015-09-13
m\modelsim\work\testbench\_primary.dbs 844 2015-09-13
m\modelsim\work\testbench\_primary.vhd 78 2015-09-13
m\modelsim\work\_info 861 2015-09-13
m\modelsim\work\_temp\vlogb2izk7 317 2014-03-10
m\modelsim\work\_temp\vlogbdqzv5 686 2014-03-10
m\modelsim\work\_temp\vlogv7idxi 688 2014-03-10
m\modelsim\work\_temp\vlogyme4yf 1444 2014-03-10
m\modelsim\work\_vmake 26 2015-09-13
m\project\db\DigitalSignalGen.(0).cnf.cdb 1408 2015-09-13
m\project\db\DigitalSignalGen.(0).cnf.hdb 778 2015-09-13
m\project\db\DigitalSignalGen.ae.hdb 8735 2014-03-11
m\project\db\DigitalSignalGen.amm.cdb 263 2015-09-13
m\project\db\DigitalSignalGen.asm.qmsg 2402 2015-09-13
m\project\db\DigitalSignalGen.asm.rdb 1344 2015-09-13
m\project\db\DigitalSignalGen.asm_labs.ddb 7014 2015-09-13
m\project\db\DigitalSignalGen.atom_map.rvd 3177 2014-03-11
m\project\db\DigitalSignalGen.cbx.xml 98 2015-09-13
m\project\db\DigitalSignalGen.cmp.bpm 562 2015-09-13
m\project\db\DigitalSignalGen.cmp.cdb 4389 2015-09-13
m\project\db\DigitalSignalGen.cmp.hdb 9602 2015-09-13
m\project\db\DigitalSignalGen.cmp.kpt 213 2015-09-13
m\project\db\DigitalSignalGen.cmp.logdb 8984 2015-09-13
m\project\db\DigitalSignalGen.cmp.rdb 15265 2015-09-13
m\project\db\DigitalSignalGen.cmp_merge.kpt 218 2015-09-13
m\project\db\DigitalSignalGen.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd 746341 2015-09-13
m\project\db\DigitalSignalGen.cycloneive_io_sim_cache.45um_tt_1200mv_0c_slow.hsd 744108 2015-09-13
m\project\db\DigitalSignalGen.cycloneive_io_sim_cache.45um_tt_1200mv_85c_slow.hsd 747089 2015-09-13
m\project\db\DigitalSignalGen.db_info 138 2014-03-11
m\project\db\DigitalSignalGen.fit.qmsg 27650 2015-09-13
m\project\db\DigitalSignalGen.hier_info 671 2015-09-13
m\project\db\DigitalSignalGen.hif 485 2015-09-13
m\project\db\DigitalSignalGen.idb.cdb 1215 2015-09-13
m\project\db\DigitalSignalGen.lpc.html 372 2015-09-13
m\project\db\DigitalSignalGen.lpc.rdb 392 2015-09-13
m\project\db\DigitalSignalGen.lpc.txt 1060 2015-09-13
m\project\db\DigitalSignalGen.map.bpm 539 2015-09-13
m\project\db\DigitalSignalGen.map.cdb 1964 2015-09-13
m\project\db\DigitalSignalGen.map.hdb 8968 2015-09-13
m\project\db\DigitalSignalGen.map.kpt 589 2015-09-13
m\project\db\DigitalSignalGen.map.logdb 4 2015-09-13
m\project\db\DigitalSignalGen.map.qmsg 5065 2015-09-13
m\project\db\DigitalSignalGen.map.rdb 1294 2015-09-13
m\project\db\DigitalSignalGen.map_bb.cdb 1038 2015-09-13
m\project\db\DigitalSignalGen.map_bb.hdb 7894 2015-09-13
m\project\db\DigitalSignalGen.map_bb.logdb 4 2015-09-13
m\project\db\DigitalSignalGen.pre_map.cdb 1710 2015-09-13
m\project\db\DigitalSignalGen.pre_map.hdb 8839 2015-09-13
m\project\db\DigitalSignalGen.root_partition.map.reg_db.cdb 205 2015-09-13
m\project\db\DigitalSignalGen.routing.rdb 1700 2015-09-13
m\project\db\DigitalSignalGen.rpp.qmsg 1995 2014-04-01
m\project\db\DigitalSignalGen.rtlv.hdb 8838 2015-09-13
m\project\db\DigitalSignalGen.rtlv_sg.cdb 1293 2015-09-13
m\project\db\DigitalSignalGen.rtlv_sg_swap.cdb 179 2015-09-13
m\project\db\DigitalSignalGen.sgate.rvd 1748 2014-04-01
m\project\db\DigitalSignalGen.sgate_sm.rvd 226 2014-04-01
m\project\db\DigitalSignalGen.sgdiff.cdb 1564 2015-09-13
m\project\db\DigitalSignalGen.sgdiff.hdb 8971 2015-09-13
m\project\db\DigitalSignalGen.sld_design_entry.sci 198 2015-09-13
m\project\db\DigitalSignalGen.sld_design_entry_dsc.sci 198 2015-09-13
m\project\db\DigitalSignalGen.smart_action.txt 5 2015-09-13
m\project\db\DigitalSignalGen.sta.qmsg 14427 2015-09-13
m\project\db\DigitalSignalGen.sta.rdb 10009 2015-09-13

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