文件名称:Xilinx_9
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Xilinx ISE
官方源代码盘第九章-Xilinx ISE official source was the ninth chapter
官方源代码盘第九章-Xilinx ISE official source was the ninth chapter
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压缩包 : 49636956xilinx_9.rar 列表 Xilinx_9 Xilinx_9\Example-9-1 Xilinx_9\Example-9-1\synplify_pro_prj Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1 Xilinx_9\Example-9-1\synplify_pro_prj\综合所需的源代码 Xilinx_9\Example-9-1\watch_sc_v5 Xilinx_9\Example-9-1\watch_sc_v5\xst Xilinx_9\Example-9-1\watch_sc_v5\xst\work Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00 Xilinx_9\Example-9-1\watch_sc_v5\_ngo Xilinx_9\Example-9-1\watch_sc_v5\_tmp_ Xilinx_9\Example-9-1\watch_sc_v5\_tmp_\coretmpdir Xilinx_9\Example-9-1\watch_sc_v5\__projnav Xilinx_9\Example-9-1\watch_sc_v6 Xilinx_9\Example-9-1\watch_sc_v6\xst Xilinx_9\Example-9-1\watch_sc_v6\xst\work Xilinx_9\Example-9-1\watch_sc_v6\xst\work\sub00 Xilinx_9\Example-9-1\watch_sc_v6\xst\work\vlg1D Xilinx_9\Example-9-1\watch_sc_v6\xst\work\vlg1E Xilinx_9\Example-9-1\watch_sc_v6\xst\work\vlg20 Xilinx_9\Example-9-1\watch_sc_v6\xst\work\vlg37 Xilinx_9\Example-9-1\watch_sc_v6\xst\work\vlg41 Xilinx_9\Example-9-1\watch_sc_v6\xst\work\vlg51 Xilinx_9\Example-9-1\watch_sc_v6\xst\work\vlg66 Xilinx_9\Example-9-1\watch_sc_v6\xst\work\vlg71 Xilinx_9\Example-9-1\watch_sc_v6\xst\work\vlg7B Xilinx_9\Example-9-1\watch_sc_v6\_ngo Xilinx_9\Example-9-1\watch_sc_v6\__projnav Xilinx_9\Example-9-1\源文件 Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\black_box.v Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\cnt60.vf Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\dcm1.v Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\decode.v Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\hex2led.v Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\outs3.vf Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\STMACH_V.v Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\stopwatch.vf Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\STMACH_V.plg Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\STMACH_V.srd Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.edf Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.fse Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.ncf Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.plg Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.srd Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.srm Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.srr Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.srs Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn\stopwatch.tlg Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.edf Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.fse Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.ncf Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.plg Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.srd Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.srm Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.srr Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.srs Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Synplify_syn_1\stopwatch.tlg Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Syn_Pro_stopwatch.prd Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Syn_Pro_stopwatch.prj Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\Syn_Pro_stopwatch.sdc Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\tenths.v Xilinx_9\Example-9-1\synplify_pro_prj\Synplify_Pro\virtex2p.v Xilinx_9\Example-9-1\synplify_pro_prj\综合所需的源代码\black_box.v Xilinx_9\Example-9-1\synplify_pro_prj\综合所需的源代码\cnt60.vf Xilinx_9\Example-9-1\synplify_pro_prj\综合所需的源代码\dcm1.v Xilinx_9\Example-9-1\synplify_pro_prj\综合所需的源代码\decode.v Xilinx_9\Example-9-1\synplify_pro_prj\综合所需的源代码\hex2led.v Xilinx_9\Example-9-1\synplify_pro_prj\综合所需的源代码\outs3.vf Xilinx_9\Example-9-1\synplify_pro_prj\综合所需的源代码\STMACH_V.v Xilinx_9\Example-9-1\synplify_pro_prj\综合所需的源代码\stopwatch.vf Xilinx_9\Example-9-1\synplify_pro_prj\综合所需的源代码\tenths.v Xilinx_9\Example-9-1\synplify_pro_prj\综合所需的源代码\virtex2p.v Xilinx_9\Example-9-1\watch_sc_v5\.untf Xilinx_9\Example-9-1\watch_sc_v5\AndNor2.sch Xilinx_9\Example-9-1\watch_sc_v5\automake.log Xilinx_9\Example-9-1\watch_sc_v5\bitgen.ut Xilinx_9\Example-9-1\watch_sc_v5\cnt60.cmd_log Xilinx_9\Example-9-1\watch_sc_v5\cnt60.jhd Xilinx_9\Example-9-1\watch_sc_v5\cnt60.sch Xilinx_9\Example-9-1\watch_sc_v5\cnt60.sym Xilinx_9\Example-9-1\watch_sc_v5\cnt60.vhf Xilinx_9\Example-9-1\watch_sc_v5\core.tpl Xilinx_9\Example-9-1\watch_sc_v5\coregen.log Xilinx_9\Example-9-1\watch_sc_v5\DCM1.jhd Xilinx_9\Example-9-1\watch_sc_v5\dcm1.sym Xilinx_9\Example-9-1\watch_sc_v5\DCM1.vhd Xilinx_9\Example-9-1\watch_sc_v5\DCM1.xaw Xilinx_9\Example-9-1\watch_sc_v5\DCM1_arwz.ucf Xilinx_9\Example-9-1\watch_sc_v5\decode.jhd Xilinx_9\Example-9-1\watch_sc_v5\decode.spl Xilinx_9\Example-9-1\watch_sc_v5\decode.sym Xilinx_9\Example-9-1\watch_sc_v5\decode.vhd Xilinx_9\Example-9-1\watch_sc_v5\decode.vhi Xilinx_9\Example-9-1\watch_sc_v5\hex2led.jhd Xilinx_9\Example-9-1\watch_sc_v5\hex2led.spl Xilinx_9\Example-9-1\watch_sc_v5\hex2led.sym Xilinx_9\Example-9-1\watch_sc_v5\hex2led.vhd Xilinx_9\Example-9-1\watch_sc_v5\hex2led.vhi Xilinx_9\Example-9-1\watch_sc_v5\outs3.cmd_log Xilinx_9\Example-9-1\watch_sc_v5\outs3.jhd Xilinx_9\Example-9-1\watch_sc_v5\outs3.sch Xilinx_9\Example-9-1\watch_sc_v5\outs3.sym Xilinx_9\Example-9-1\watch_sc_v5\outs3.vhf Xilinx_9\Example-9-1\watch_sc_v5\readme.txt Xilinx_9\Example-9-1\watch_sc_v5\stmach_v.dia Xilinx_9\Example-9-1\watch_sc_v5\STMACH_V.jhd Xilinx_9\Example-9-1\watch_sc_v5\stmach_v.spl Xilinx_9\Example-9-1\watch_sc_v5\stmach_v.sym Xilinx_9\Example-9-1\watch_sc_v5\STMACH_V.vhd Xilinx_9\Example-9-1\watch_sc_v5\stmach_v.vhi Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.ana Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.bgn Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.bit Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.bld Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.cmd_log Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.dly Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.drc Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.jhd Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.mrp Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.nc1 Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.ncd Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.ngc Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.ngd Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.ngm Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.ngr Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.pad Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.par Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.pcf Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.prj Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.sch Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.schbak Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.schcmd Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.sprj Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.stx Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.sym Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.syr Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.twr Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.twx Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.ut Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.vhdsim_xlate Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.vhf Xilinx_9\Example-9-1\watch_sc_v5\stopwatch.xpi Xilinx_9\Example-9-1\watch_sc_v5\stopwatch_map.ncd Xilinx_9\Example-9-1\watch_sc_v5\stopwatch_map.ngm Xilinx_9\Example-9-1\watch_sc_v5\stopwatch_ngdbuild.nav Xilinx_9\Example-9-1\watch_sc_v5\stopwatch_tb.jhd Xilinx_9\Example-9-1\watch_sc_v5\stopwatch_tb.vhd Xilinx_9\Example-9-1\watch_sc_v5\stopwatch_translate.vhd Xilinx_9\Example-9-1\watch_sc_v5\tenths.asy Xilinx_9\Example-9-1\watch_sc_v5\tenths.coregen_log Xilinx_9\Example-9-1\watch_sc_v5\tenths.edn Xilinx_9\Example-9-1\watch_sc_v5\tenths.jhd Xilinx_9\Example-9-1\watch_sc_v5\tenths.ngo Xilinx_9\Example-9-1\watch_sc_v5\tenths.sym Xilinx_9\Example-9-1\watch_sc_v5\tenths.v Xilinx_9\Example-9-1\watch_sc_v5\tenths.veo Xilinx_9\Example-9-1\watch_sc_v5\tenths.vhd Xilinx_9\Example-9-1\watch_sc_v5\tenths.vho Xilinx_9\Example-9-1\watch_sc_v5\tenths.xco Xilinx_9\Example-9-1\watch_sc_v5\tenths.xcp Xilinx_9\Example-9-1\watch_sc_v5\tenths_flist.txt Xilinx_9\Example-9-1\watch_sc_v5\userlang.tpl Xilinx_9\Example-9-1\watch_sc_v5\watch.sch Xilinx_9\Example-9-1\watch_sc_v5\wtut_sc.npl Xilinx_9\Example-9-1\watch_sc_v5\wtut_sc.ptf Xilinx_9\Example-9-1\watch_sc_v5\xst\work\hdpdeps.ref Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl00.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl01.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl02.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl03.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl04.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl05.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl06.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl07.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl08.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl09.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl10.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl11.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl12.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl13.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl14.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl15.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl16.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl17.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl18.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\sub00\vhpl19.vho Xilinx_9\Example-9-1\watch_sc_v5\xst\work\vhdllib.ref Xilinx_9\Example-9-1\watch_sc_v5\_ngo\netlist.lst Xilinx_9\Example-9-1\watch_sc_v5\_ngo\tenths.ngo Xilinx_9\Example-9-1\watch_sc_v5\__projnav\bitgen.rsp Xilinx_9\Example-9-1\watch_sc_v5\__projnav\ednTOngd_tcl.rsp Xilinx_9\Example-9-1\watch_sc_v5\__projnav\map.log Xilinx_9\Example-9-1\watch_sc_v5\__projnav\mapFloorPlanner.rsp Xilinx_9\Example-9-1\watch_sc_v5\__projnav\nc1TOncd_tcl.rsp Xilinx_9\Example-9-1\watch_sc_v5\__projnav\ngd2vhdl.log Xilinx_9\Example-9-1\watch_sc_v5\__projnav\p007m000.kis Xilinx_9\Example-9-1\watch_sc_v5\__projnav\p00p5000.kis Xilinx_9\Example-9-1\watch_sc_v5\__projnav\p00pz000.kis Xilinx_9\Example-9-1\watch_sc_v5\__projnav\par.log Xilinx_9\Example-9-1\watch_sc_v5\__projnav\posttrc.log Xilinx_9\Example-9-1\watch_sc_v5\__projnav\runXst_tcl.rsp Xilinx_9\Example-9-1\watch_sc_v5\__projnav\stopwatch.err Xilinx_9\Example-9-1\watch_sc_v5\__projnav\stopwatch.xst Xilinx_9\Example-9-1\watch_sc_v5\__projnav\stopwatch._prj Xilinx_9\Example-9-1\watch_sc_v5\__projnav\stopwatch._sprj Xilinx_9\Example-9-1\watch_sc_v5\__projnav\stopwatch_ncdTOut_tcl.rsp Xilinx_9\Example-9-1\watch_sc_v5\__projnav\tb.rsp Xilinx_9\Example-9-1\watch_sc_v5\__projnav\wtut_sc.gfl Xilinx_9\Example-9-1\watch_sc_v5\__projnav\wtut_sc_flowplus.gfl Xilinx_9\Example-9-1\watch_sc_v5\__projnav.log Xilinx_9\Example-9-1\watch_sc_v6\.untf Xilinx_9\Example-9-1\watch_sc_v6\AndNor2.sch Xilinx_9\Example-9-1\watch_sc_v6\automake.log Xilinx_9\Example-9-1\watch_sc_v6\bitgen.ut Xilinx_9\Example-9-1\watch_sc_v6\cnt60.sch Xilinx_9\Example-9-1\watch_sc_v6\cnt60.sym Xilinx_9\Example-9-1\watch_sc_v6\cnt60.vf Xilinx_9\Example-9-1\watch_sc_v6\core.tpl Xilinx_9\Example-9-1\watch_sc_v6\coregen.log Xilinx_9\Example-9-1\watch_sc_v6\coregen.prj Xilinx_9\Example-9-1\watch_sc_v6\DCM1.spl Xilinx_9\Example-9-1\watch_sc_v6\dcm1.sym Xilinx_9\Example-9-1\watch_sc_v6\DCM1.tfi Xilinx_9\Example-9-1\watch_sc_v6\dcm1.v Xilinx_9\Example-9-1\watch_sc_v6\DCM1.vhd Xilinx_9\Example-9-1\watch_sc_v6\dcm1.xaw Xilinx_9\Example-9-1\watch_sc_v6\dcm1_arwz.ucf Xilinx_9\Example-9-1\watch_sc_v6\DCM1_jhdparse_tcl.rsp Xilinx_9\Example-9-1\watch_sc_v6\dcm_1.xaw Xilinx_9\Example-9-1\watch_sc_v6\decode.spl Xilinx_9\Example-9-1\watch_sc_v6\decode.sym Xilinx_9\Example-9-1\watch_sc_v6\decode.vhd Xilinx_9\Example-9-1\watch_sc_v6\hex2led.spl Xilinx_9\Example-9-1\watch_sc_v6\hex2led.sym Xilinx_9\Example-9-1\watch_sc_v6\hex2led.vhd Xilinx_9\Example-9-1\watch_sc_v6\outs3.sch Xilinx_9\Example-9-1\watch_sc_v6\outs3.sym Xilinx_9\Example-9-1\watch_sc_v6\outs3.vf Xilinx_9\Example-9-1\watch_sc_v6\pepExtractor.prj Xilinx_9\Example-9-1\watch_sc_v6\stmach_v.dia Xilinx_9\Example-9-1\watch_sc_v6\stmach_v.spl Xilinx_9\Example-9-1\watch_sc_v6\stmach_v.sym Xilinx_9\Example-9-1\watch_sc_v6\STMACH_V.vhd Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.bgn Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.bit Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.bld Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.cmd_log Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.drc Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.lso Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.mrp Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.nc1 Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.ncd Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.ngc Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.ngd Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.ngm Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.ngr Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.pad Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.pad_txt Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.par Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.pcf Xilinx_9\Example-9-1\watch_sc_v6\stopwatch.placed_ncd_tracker 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