搜索资源列表
bist
- 芯片测试讲义，讲的BIST内容。 即芯片的自测。
BIST_Circuits
- BIST 电路IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-BIST circuits IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
bist
- 芯片测试讲义，讲的BIST内容。 即芯片的自测。-Chip test notes, the contents of said BIST. That is, self-rated chips.
ElectronicTesting
- 数字存储器和混合信号超大规模集成电路 本书系统地介绍了数字、存储器和混合信号VLSI系统的测试和可测试性设计。该书是根据作者多年的科研成果和教学实践，结合国际上关注的最新研究热点并参考大量的文献撰写的。全书共分三个部分。第一部分是测试基础，介绍了测试基本概念、测试设备、测试经济学和故障模型。第二部分是测试方法，详细论述了组合和时序电路的测试生成、存储器测试、基于DSP和基于模块的模拟与混合信号测试、延迟测试和IDDQ测试等。第三部分
DFT_BIST_for_SOC
- 用于SoC设计的DFT和BIST，讲解了在SOC设计中需要考虑的可测性设计问题 -SoC design for DFT and BIST, explain in the SOC design need to consider design-for-test issues
dokserv
- A BIST (BUILT-IN SELF-TEST) STRATEGY FOR MIXED-SIGNAL INTEGRATED CIRCUITS
getPDF
- 本文分析的环境，利用内建自测试（ BIST ）和自动测试设备（ ATE ）和提出了封闭形式表达的故障覆盖率的函数数量的BIST的和ATE测试向量。-Analysis and Measurement of Fault Coverage in a Combined ATE and BIST Environment
fwrememorybistvcestudent
- bist method for simulation of micro controller
bist
- design for test Test and Design-for-Test for memory bist-design for test
BISTProject
- BIST test doing project, in verilog.
uart
- UART design with bist capability
BIST
- A simple BIST in VHDL. It contains a LFSR with an SISR.
LIP2908CORE_membist
- Mem bist Verilog Module
FPGST
- FPGA的时延故障测试方法 BIST的动态可重构-FPGA delay fault test method of dynamically reconfigurable BIST
rage
- 逻辑内建自测试高故障覆盖率设计Logic BIST design of high fault coverage-Logic BIST design of high fault coverage
rategy
- FPGA的板级BIST设计和实现策略FPGA board-level BIST design and implementation strategy-FPGA board-level BIST design and implementation strategy
doc
- BIST for RAMs using ASTRA: Transparent Built-In Self Test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction
BIST-CODE
- BIST IS A BUILT IN SELF TEST FOR VHDL
bist 2017 paper
- A new low-power (LP) scan-based built-in selftest (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudora
bist pattern generator
- document of bist with low power generator