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VERIOGCLK
- 作clk_in 的二分频clk_out，要求输出与上例的输出正好反相。编写测试模块， 给出仿真波形。-clk_in for the two-frequency clk_out, output and demand were on the output is reverse. Test preparation module, simulation waveforms are given.
clk_d
- ccs中有关时钟的源代码，已经经过调试，可以直接运行-ccs clock on the source code, after debugging, and can directly run
VERIOGCLK
- 作clk_in 的二分频clk_out，要求输出与上例的输出正好反相。编写测试模块， 给出仿真波形。-clk_in for the two-frequency clk_out, output and demand were on the output is reverse. Test preparation module, simulation waveforms are given.
pci_arbi_quicklogic
- PCI 仲裁代码/ PCI BUS ARBITER //WRITTEN BY MARIA GEORGE `include "c:\pasic\spde\data\macros.v" module Arbiter (REQ_, reset_, clk_in, fr a me_, irdy_, GNT_, adbus, cbe) parameter MASTERS = 6 //This code can
5509ATestingCode
- 这是实验室买的瑞泰DSP5509开发板所戴的实验代码，里面包含了DSP基本的实验代码，比较适合刚刚学习DSP的初学者-This is the lab bought Skandia DSP5509 development board are wearing the experiment code, which contains the basic experimental DSP code, more suitable for begin
clkdiv
- -- Clock divider of generic width (default = 4 bits) -- based on counter from Library of Parameterized Modules (LPM) -- Accepts clock signal at clk_in -- Output clk_out has frequency of clk_in/(2^width) -- Specif
LIBRARY-IEEE
- 加法计数器的设计 任意进制的计数器设计-LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY sun IS PORT(ENA,CLK_IN,CLR:IN STD_LOGIC Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0) ) END sun ARCHITECTURE A OF sun IS SIGNAL CLK:
7_1
- 电路端口为：异步清零输入端口rst，输入时钟clk_in，输出时钟clk_out。并分别采用两种以上的方法实现。(Frequency divider circuit port is: Asynchronous Clear input port rst, input clock clk_in, output clock clk_out. And use two or more methods to achieve.)