搜索资源列表
my_ramlib_06
- 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL descr iption, such as FIFO, Dual Port RAM, etc.
4VerilogFIFO
- 一种新的FIFO实现方法,verilog描述，通过modelsim 6.0 仿真，Quartue综合-FIFO realize a new method, verilog descr iption, modelsim 6.0 through simulation, Quartue integrated
16550
- UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。-UART16550 compatible serial communication controller, Verilog language descr iption, the use of Altera Cyclone series FPGA
ref-sdr-sdram-verilog
- SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
FIFO
- 异步FIFO的实现，可综合，可验证] keywords:almost_full,full,almost_empty,empty-The realization of asynchronous FIFO can be comprehensive, verifiable] keywords: almost_full, full, almost_empty, empty
FIFO
- 通用异步FIFO设计的verilog代码，来自于opencore-Universal Asynchronous FIFO Verilog design code, from opencore
lcd-code
- 比较完整的LCD接口代码，verilog编写，分为6800和8080两种CPU接口，且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program
FIFO1
- FIFO存储电路的设计与实现，用verilog实现fifo的参考设计-FIFO memory circuit design and realization of the realization of fifo with Verilog reference design
asyn_fifo
- verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
FIFO
- 用VERILOG写的FIFO程序，可以直接引用经本人测试-VERILOG written using FIFO procedures, can be directly invoked by the I test
fifo_src
- verilog语言实现，利用BlockRAM实现FIFO。-Verilog language, the use of BlockRAM achieve FIFO.
FPGA_FIFO
- 使用Verilog编写的同步FIFO，可通过设置程序中的DEPTH设置FIFO的深度，FIFO_WRITE_CLOCK上升沿向FIFO中写入数据， FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH sett
FIFO
- 512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
fifo8
- FIFO 源程序，verilog HDL实现，自己验证过，没问题-FIFO source, verilog HDL to achieve their own verified, no problem
FIFO
- 利用Verilog实现了一个FIFO，包含几个模块文件，适合初学Verilog的朋友，含测试代码。-Verilog achieved using a FIFO, a document contains several modules, suitable for novice Verilog friends, including test code.
68013_SlaveFIFO
- cy7c68013工作在SLAVE FIFO下的FPGA源代码，已经通过，Verilog编写-cy7c68013 slave fifo mode code ,written by hard ware language
async_fifo
- verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
Verilog
- 异步fifo的经典写法，使用verilog语言编写的。-Asynchronous fifo' s classic formulation, using verilog language.
FIFO
- verilog编写的读写fifo的源码，包括sram的读写控制-verilog source code written to read and write fifo, including the sram to read and write control
fifo-verilog
- 自己设计的一种FIFO寄存器，用verilog 编写，QUARTUS II下验证-Own design of a FIFO register, with verilog preparation, QUARTUS II certification under