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fifo
- 这篇文档主要是描述了fifo的作用,里面有用verilog写的源码,及其综合后的结果-This document mainly describes the role of the FIFO inside useful verilog to write source code, and its consolidated results
sync-and-asyn_FIFO_verilog
- 同步与异步FIFO的verilog实现,包括源代码,testbench,测试以及综合通过,还有相关参考资料-Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references
myuart
- 使用verilog语言编写的异步串口模块,带有16级深的FIFO,它与DSP28335的SCI相似,可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to u
FIFO
- 将ROM的正弦波数据输入FIFO存储器,然后输出,有modelsim仿真波形-Verilog FIFO ROM mif sine
FIFO
- 基于FPGA的8位fifo 1s发送10个8位数据,采用的是verilog 编程语言,入门,方便各位学习-Eight fifo based on FPGA 1 s sent 10 8 bits of data, USES is verilog programming language, introduction, convenient for you to learn
t4_fifo
- FIFO的verilog与VHDL的实现,并与FIFO的IP核做对比,为了方便大家学习,每个文件均附有测试脚本文件,希望对大家有用。-The FIFO verilog and VHDL implementation with FIFO IP core to do comparison, in order to facilitate learning, each file with a test scr ipt file, we want
async_fifo-and-verilog
- 异步fifo的详细原理分析说明及verilog源代码,经典推荐!-Detailed descr iption of the principles and analysis of asynchronous fifo verilog source code, the classic recommendation!
syn_fifo_style_2
- 由verilog实现的,异步FIFO,分为多模块实现。-Verilog achieved by the asynchronous FIFO, divided into multiple modules.
SLAVE-FIFO-16BITS
- CY7C68013a的slavefifo的固件源代码,keil编写,以及使用FPGA向EP6端点写数据的verilog源代码,没有错误,可以编译成功!-CY7C68013a of slavefifo firmware source code, keil prepared using FPGA and write data to the endpoint EP6 verilog source code, no errors, you ca
spi_cbb
- 基于FPGA设计,verilog语言变成的,SPI通用接口模块,顶层已封装成类似标准的FIFO接口;提供仿真文件;仿真器为modelsim10.0c,波形观察debussy。-Based on the FPGA design, Verilog language into a, SPI universal interface module, the top has been packaged into a FIFO interface s
UART_RX
- 这是借鉴别人的带有FIFO的Verilog代码分享给大家,共同学习-This is learn from others with FIFO Verilog code for everyone to share, learn together
fifo
- 基于Verilog的fifo源码,经验证,有效,实用-very good
async_fifo_prj
- Verilog语言写的异步fifo,包含随机数产生电路和testbentch,直接可用于实际工程中。代码为华为内部代码。相信你会喜欢。-Verilog language used to write asynchronous fifo, including random number generation circuit and testbentch, can be used directly in the actual project.
aFifo
- 异步fifo用verilog语言实现的完整代码,适用于数字前端的设计-This implementation is based on the article Asynchronous FIFO
FIFO1
- 给出一个位宽16比特,深度为10的异步FIFO的设计,并要求给出空或满的指示信号。要求用Verilog HDL语言设计,并编写测试激励,以及用Modelsim进行功能仿真,验证设计正确性。10个16位的数据 (FIFO的宽度:也就是英文资料里常看到的THE WIDTH,它指的是FIFO一次读写操作的数据位,就像MCU有8位和16位,ARM 32位等等。FIFO的深度:THE DEEPTH,它指的是FIFO可以存储多少个N位的数
FIFO
- 用verilog语言编写的FIFO文件,这是一种传统的按序执行方法,先进入的指令先完成并引退,跟着才执行第二条指令,希望能够帮助读者-With verilog language FIFO file, which is a traditional sequential execution method, first enter the command to finish and retire, followed by only the s
Buf_FiFo
- verilog 编写的FIFO,里边有IP核和控制模块,-verilog write FIFO, inside the IP core and control module,
sp6ex19
- FPGA片内FIFO实例,对FPGA片内FIFO进行读写测试(FPGA examples of FIFO, FPGA on-chip FIFO reading and writing test)
asyn_fifo_204b_28
- 通用性异步fifo,性能非常好,推荐给大家(unverisal asyn fifo)
sdtest
- 这个是一个verilog程序,可以用spi读取sd卡中的内容,存到fifo中(This project can read the data from SD card through SPI interface and store the data in FIFO.)