搜索资源列表
sinfasheng
- 正弦信号发生器（可扫频）通过验证 正弦信号发生器-Sinusoidal signal generator (which can be swept) through the validation of sinusoidal signal generator
rng
- verilog编写随机数产生源程序，在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的-random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the
crc
- CRC码产生器与校验器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or asynchronous reset-CRC code ge
DDS
- 用8051控制DDS信号发生器，产生1HZ-10MHz的正弦波/三角波/方波-DDS with 8051 control signal generator, producing the 1HZ-10MHz sine/triangle/square wave
bt860
- 一种多制式电视信号发生器，包含多种格式，可产生PAL、NTSC、SECAM下的各种信号-A multi-system television signal generator, including a variety of formats, can produce PAL, NTSC, SECAM, under a variety of signal
convolutional_encode
- simulating a convolutional encoder allows the user to input a source code to be encoded and also input the values of the generator polynomials. It outputs the encoded data bits, where 1/n is the code rate
Rayleigh_Fading_Channel_Signal_Generator
- Rayleigh Fading Channel Signal Generator
xinhaofashengqi
- 简易信号发生器，可产生正弦波、方波、三角波，幅度、频率都可调节。-Simple signal generator can produce sine, square, triangle wave, amplitude, frequency adjustment can be.
DDS
- 基于DDS原理的正弦信号发生器。用VERILOG语言实现，功能强大。-DDS based on the principle of sinusoidal signal generator. Using Verilog language and powerful.
rng_opencore
- opencore, random number generator, verilog
PN_GEN
- 一个PN序列发生器，大M序列，供参考学习，-A PN sequence generator, the M series, for reference study,
VGADIY
- 自己编的VGA彩条信号发生器verilog ise环境-Own the VGA color signal generator verilog ise Environment
LFSR
- 伪随机序列产生器,线性反馈移位寄存器，原代码。-Pseudo-random sequence generator, linear feedback shift register, the original code.
lfsr
- 伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.
fcsr
- 伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
ffcsr
- 伪随机序列产生器－filtered 代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.
dfi
- 感应双馈发电机系统的仿真,已经完美封装好,参数可自行更改.-Doubly-fed induction generator system simulation, has the perfect package, and can make changes to parameters.
DDS
- 基于DDS技术的函数波形发生器设计，适合用fpga设计波形发生器用-Based on DDS technology function waveform generator design, suitable for FPGA design with Waveform Generator
codesyskeygen
- codesys keygen 著名工控软件CODESYS的序列号生成器-industrial control software codesys keygen CoDeSys famous serial number generator
sine-generator
- 原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成，可产生正弦波。更改rom内容可改变波形-Original: Using VHDL languages sinusoidal signal generator. rom using Quartus LPM s own generation, can produce sine wave. Rom content changes can change the