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seq_gen_576
- 高清电视HDTV信号发生器，576P逐行，VHDL语言，ALTERA的Quartus II开发平台-HDTV HDTV signal generator, 576P progressive, VHDL, Altera's Quartus II development platform
counter60
- 这是我们做的一个作业 摸60计数器，用Quartus ii 做的 ，内容齐全 不可不看。-This is the one we do feel 60 counter operation with Quartus ii do. complete contents can not see.
videofram
- 用CPLD控制图像卡进行帧存逻辑的verilog程序,用Quartus II 5.0打开-with CPLD control image fr a me buffer cards logical verilog procedures, Quartus II 5.0 Open
altera_lcd_controller
- quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE
VHDL_Memory_Library_Code
- 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
CrackQII60
- quartus6.0+nios2 6.0的License,将hostid改为你自己的网卡号即可使用quartus和nios6.0的全部功能-quartus6.0 nios2 6.0 License, hostid to read your own card can be used quartus, and the full functionality of nios6.0
Crack_QII60_b178
- Quartus II 6.0完全Crack文件-Quartus II 6.0 document completely Crack
23565785scan_led
- Quartus环境下的7段扫描显示电路的源程序-Quartus environment of the seven scanning display circuit of the source
234352325DECL7S
- Quartus环境下的7段译码管的扫描显示电路-Quartus environment of the seven decoding of the scan show circuit
ddsquartus
- 使用QUARTUS 2编译的DDS的源码-QUARTUS use two compiled the DDS source
verilog50%
- 本文主要介绍了50％占空比三分频器的三种设计方法，并给出了图形设计、VHDL设计、编译结果和仿真结果。设计中采用EPM7064AETC44-7 CPLD，在QUARTUSⅡ4.2软件平台上进行。 -This paper introduces a 50% duty cycle three dividers of the three design methods, and gives the graphic design, VHDL d
nios_uart
- 基于Nios II的串口通信，在quartus的开发环境中进行的实验-based Nios II Serial Communication in quartus development environment for the conduct of the experiment
38encode
- 三八译码器的源代码，在quartus II 6.0中进行进行设计的，有vhdl源代码-March 8 decoder source code, in quartus II 6.0 for the design, Source code is vhdl
SVGA_quartus
- 在开发板上实现svga条形信号发生器的源代码，是在quartus II 6.0的开发环境中运行的-achieved in the development of board svga strip signal generator source code, in quartus II 6.0 development environment running on
656to601
- 本程序实现视频图象的CCIR656转换CCIR601格式,使用的环境是Quartus II 4.0-the program CCIR656 video image conversion CCIR601 format, The environment is the use of Quartus II 4.0
lcd4quartus
- 128×64单色点阵LCD的quartus工程文件-128 x 64 monochrome dot-matrix LCD quartus works documents
3des-VHDL
- 3des的VHDL实现，适用于quartus环境-3des VHDL applicable to the environment quartus
AlteraQuartusII6.0crack
- Altera Quartus II 6.0 破解文件-Altera Quartus II 6.0 crack documents
2FSK2psk
- ２ＦＳＫ２ＰＳＫ－二进制频移键控和相移键控信号发生器的源程序，是基于ＱＵＡＲＴＵＳ ＩＩ软件平台，使用ＶＨＤＬ语言-2FSK2PSK-binary frequency shift keying and phase shift keying signal generator source, QUARTUS II is based on the software platform, the use of VHDL
q2_7_license
- altera quartus 2 7.0 许可文件-altera quartus 2 7.0 permit documents